Lines Matching full:instruction

3 …"PublicDescription": "Instruction architecturally executed, Condition code check pass, software in…
6 …"BriefDescription": "Instruction architecturally executed, Condition code check pass, software inc…
9         "PublicDescription": "Level 1 instruction cache refill",
12         "BriefDescription": "Level 1 instruction cache refill"
15         "PublicDescription": "Attributable Level 1 instruction TLB refill",
18         "BriefDescription": "Attributable Level 1 instruction TLB refill"
39 …      "PublicDescription": "Instruction architecturally executed, condition code check pass, load",
42         "BriefDescription": "Instruction architecturally executed, condition code check pass, load"
45 …     "PublicDescription": "Instruction architecturally executed, condition code check pass, store",
48         "BriefDescription": "Instruction architecturally executed, condition code check pass, store"
51         "PublicDescription": "Instruction architecturally executed",
54         "BriefDescription": "Instruction architecturally executed"
63 …"PublicDescription": "Instruction architecturally executed, condition check pass, exception return…
66 … "BriefDescription": "Instruction architecturally executed, condition check pass, exception return"
69 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CO…
72 …"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CON…
75 …"PublicDescription": "Instruction architecturally executed, condition code check pass, software ch…
78 …"BriefDescription": "Instruction architecturally executed, condition code check pass, software cha…
81         "PublicDescription": "Instruction architecturally executed, immediate branch",
84         "BriefDescription": "Instruction architecturally executed, immediate branch"
87 …"PublicDescription": "Instruction architecturally executed, condition code check pass, procedure r…
90 …"BriefDescription": "Instruction architecturally executed, condition code check pass, procedure re…
93 … "PublicDescription": "Instruction architecturally executed, condition code check pass, unaligned",
96 …   "BriefDescription": "Instruction architecturally executed, condition code check pass, unaligned"
123         "PublicDescription": "Attributable Level 1 instruction cache access",
126         "BriefDescription": "Attributable Level 1 instruction cache access"
171 …"PublicDescription": "Instruction architecturally executed, Condition code check pass, write to TT…
174 …"BriefDescription": "Instruction architecturally executed, Condition code check pass, write to TTB…
195         "PublicDescription": "Instruction architecturally executed, branch",
198         "BriefDescription": "Instruction architecturally executed, branch"
201         "PublicDescription": "Instruction architecturally executed, mispredicted branch",
204         "BriefDescription": "Instruction architecturally executed, mispredicted branch"
225         "PublicDescription": "Attributable Level 1 instruction TLB access",
228         "BriefDescription": "Attributable Level 1 instruction TLB access"
255         "PublicDescription": "Attributable Level 2 instruction TLB refill.",
258         "BriefDescription": "Attributable Level 2 instruction TLB refill."
267         "PublicDescription": "Attributable Level 2 instruction TLB access.",
270         "BriefDescription": "Attributable Level 2 instruction TLB access."
285         "PublicDescription": "Access to instruction TLB that causes a translation table walk",
288         "BriefDescription": "Access to instruction TLB that causes a translation table walk"
327 …  The counter counts every attributable cycle on which no attributable instruction or operation wa…
333 …backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation wa…
339 …LL_SLOT where no attributable instruction or operation was sent for execution because there was no…
345 …on each attributable cycle the number of instruction or operation slots that were not occupied by …
387 …instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter c…
390         "BriefDescription": "Level 1 instruction cache long-latency read miss"
513         "PublicDescription": "SIMD Instruction architecturally executed.",
516         "BriefDescription": "SIMD Instruction architecturally executed."
519         "PublicDescription": "Instruction architecturally executed, SVE.",
522         "BriefDescription": "Instruction architecturally executed, SVE."