Lines Matching full:access

27         "PublicDescription": "Level 1 data cache access",
30         "BriefDescription": "Level 1 data cache access"
117         "PublicDescription": "Data memory access",
120         "BriefDescription": "Data memory access"
123         "PublicDescription": "Attributable Level 1 instruction cache access",
126         "BriefDescription": "Attributable Level 1 instruction cache access"
135         "PublicDescription": "Level 2 data cache access",
138         "BriefDescription": "Level 2 data cache access"
153         "PublicDescription": "Attributable Bus access",
156         "BriefDescription": "Attributable Bus access"
219         "PublicDescription": "Attributable Level 1 data or unified TLB access",
222         "BriefDescription": "Attributable Level 1 data or unified TLB access"
225         "PublicDescription": "Attributable Level 1 instruction TLB access",
228         "BriefDescription": "Attributable Level 1 instruction TLB access"
243         "PublicDescription": "Attributable Level 3 data cache access",
246         "BriefDescription": "Attributable Level 3 data cache access"
261         "PublicDescription": "Attributable Level 2 data or unified TLB access",
264         "BriefDescription": "Attributable Level 2 data or unified TLB access"
267         "PublicDescription": "Attributable Level 2 instruction TLB access.",
270         "BriefDescription": "Attributable Level 2 instruction TLB access."
273         "PublicDescription": "Access to another socket in a multi-socket system",
276         "BriefDescription": "Access to another socket in a multi-socket system"
279         "PublicDescription": "Access to data TLB causes a translation table walk",
282         "BriefDescription": "Access to data TLB causes a translation table walk"
285         "PublicDescription": "Access to instruction TLB that causes a translation table walk",
288         "BriefDescription": "Access to instruction TLB that causes a translation table walk"
303 … "PublicDescription": "Attributable memory read access to another socket in a multi-socket system",
306 …   "BriefDescription": "Attributable memory read access to another socket in a multi-socket system"
309 … data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CAC…
387 …access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from…
393 …access counted by L2D_CACHE that incurs additional latency because it returns data from outside th…
399 …access counted by L3D_CACHE that incurs additional latency because it returns data from outside th…
477         "PublicDescription": "Access with additional latency from alignment",
480         "BriefDescription": "Access with additional latency from alignment"
495         "PublicDescription": "Checked data memory access",
498         "BriefDescription": "Checked data memory access"
501         "PublicDescription": "Checked data memory access, read",
504         "BriefDescription": "Checked data memory access, read"
507         "PublicDescription": "Checked data memory access, write",
510         "BriefDescription": "Checked data memory access, write"