Lines Matching full:of

5 …ranches that are never resolved because they are in the misprediction shadow of an earlier branch",
14 "ScaleUnit": "100percent of bus cycles"
19 … ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. T…
26of level 1 instruction cache accesses missed to the total number of level 1 instruction cache acce…
40 …s the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This g…
75 …"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operat…
77 "ScaleUnit": "100percent of operations"
82 …"BriefDescription": "This metric measures crypto operations as a percentage of operations speculat…
84 "ScaleUnit": "100percent of operations"
95 …"BriefDescription": "This metric measures scalar integer operations as a percentage of operations …
97 "ScaleUnit": "100percent of operations"
102 "BriefDescription": "This metric measures the number of instructions retired per cycle.",
109 …"BriefDescription": "This metric measures load operations as a percentage of operations speculativ…
111 "ScaleUnit": "100percent of operations"
116 …"BriefDescription": "The rate of load or store instructions speculatively executed to overall inst…
118 "ScaleUnit": "100percent of operations"
123 "BriefDescription": "Millions of instructions per second",
129 "BriefDescription": "Millions of instructions per second",
135 …"BriefDescription": "The rate of software change of the PC speculatively executed to overall instr…
137 "ScaleUnit": "100percent of operations"
142 …"BriefDescription": "This metric measures store operations as a percentage of operations speculati…
144 "ScaleUnit": "100percent of operations"
149 …n": "This metric measures scalar floating point operations as a percentage of operations speculati…
151 "ScaleUnit": "100percent of operations"
156 … "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
163 "BriefDescription": "Of all the micro-operations issued, what proportion are lost",
170 …"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed…
177 …"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache mi…
179 "ScaleUnit": "100percent of cycles"
184 …"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource…
186 "ScaleUnit": "100percent of cycles"
191 …"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss…
193 "ScaleUnit": "100percent of cycles"
198 …"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache mis…
200 "ScaleUnit": "100percent of cycles"
205 …"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
207 "ScaleUnit": "100percent of cycles"
212 …ic measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an in…
219 …ures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This give…
233 "BriefDescription": "Fraction of slots lost due to misspeculation",
236 "ScaleUnit": "100percent of slots"
241 "BriefDescription": "Fraction of slots retiring, useful work",
244 "ScaleUnit": "100percent of slots"
249 …"BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem iss…
256 …"BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues …
263 "BriefDescription": "Fraction of slots lost due to branch misprediciton",
265 "ScaleUnit": "1percent of slots"
270 …"BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispat…
272 "ScaleUnit": "1percent of slots"
277 …"BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/t…
279 "ScaleUnit": "100percent of slots"
284 … "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
286 "ScaleUnit": "1percent of slots"
291 "BriefDescription": "Fraction of execute slots utilized",
293 "ScaleUnit": "1percent of slots"
298 "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
300 "ScaleUnit": "100percent of cycles"
305 "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
307 "ScaleUnit": "100percent of cycles"
312 "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
314 "ScaleUnit": "100percent of cycles"
319 "BriefDescription": "Fraction of FSU execute slots utilized",
321 "ScaleUnit": "100percent of slots"
326 "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
328 "ScaleUnit": "100percent of slots"
333 "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
335 "ScaleUnit": "100percent of slots"
340 "BriefDescription": "Fraction of IXU execute slots utilized",
342 "ScaleUnit": "100percent of slots"
347 "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
349 "ScaleUnit": "100percent of slots"
354 "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
356 "ScaleUnit": "100percent of cycles"
361 "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
363 "ScaleUnit": "100percent of cycles"
368 "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
370 "ScaleUnit": "100percent of cycles"
375 "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
377 "ScaleUnit": "100percent of cycles"
382 "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
384 "ScaleUnit": "100percent of cycles"
391 "ScaleUnit": "100percent of cache acceses"
398 "ScaleUnit": "100percent of cache acceses"
405 "ScaleUnit": "100percent of cache acceses"
412 "ScaleUnit": "100percent of cache acceses"
419 "ScaleUnit": "100percent of cache acceses"
426 "ScaleUnit": "100percent of cache acceses"
431 …"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_…
433 "ScaleUnit": "100percent of cache acceses"
438 …"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_…
440 "ScaleUnit": "100percent of cache acceses"