perf/Documentation/perf-intel-pt.txt

266 So, to disable TSC packets use:
319 tsc		Always supported.  Produces TSC timestamp packets to provide
371 		Because a TSC packet is produced with PSB, the PSB period can
377 		MTC packets provide finer grain timestamp information than TSC
379 		clock (CTC) which is related to TSC packets using a TMA packet.
408 		can be related to TSC via values provided in cpuid leaf 0x15.
422 		MTC and TSC packets.  A CYC packet contains the number of CPU
423 		cycles since the last CYC packet. Unlike MTC and TSC packets,
887 Note also, the sched_switch event is only added if TSC packets are requested.
1030 "ns" (nanoseconds), "t" (TSC ticks) or "i" (instructions).
1032 "ms", "us" and "ns" are converted to TSC ticks.
1037 on the sample is *not* adjusted and reflects the last known value of TSC.
1147 The Z option is equivalent to having recorded a trace without TSC
1260 (i.e. no TSC timestamps) or VM Time Correlation. VM Time Correlation is an extra step
1261 using 'perf inject' and requires unchanging VMX TSC Offset and no VMX TSC Scaling.
1300 TSC is not supported and tsc=0 must be specified.  That means mtc is useless, so add mtc=0.
1372 Now 'perf inject' can be used to determine the VMX TCS Offset. Note, Intel PT TSC packets are
1373 only 7-bytes, so the TSC Offset might differ from the actual value in the 8th byte. That will
1377  ERROR: Unknown TSC Offset for VMCS 0x1bff6a
1378  VMCS: 0x1bff6a  TSC Offset 0xffffe42722c64c41
1379  ERROR: Unknown TSC Offset for VMCS 0x1cbc08
1380  VMCS: 0x1cbc08  TSC Offset 0xffffe42722c64c41
1381  ERROR: Unknown TSC Offset for VMCS 0x1c3ce8
1382  VMCS: 0x1c3ce8  TSC Offset 0xffffe42722c64c41
1383  ERROR: Unknown TSC Offset for VMCS 0x1cbce9
1384  VMCS: 0x1cbce9  TSC Offset 0xffffe42722c64c41
1387 shown above with the calculated TSC Offset. For an unchanging TSC Offset
1390 Now that the TSC Offset is known, it can be provided to 'perf inject'
1396  [ dry-run ] [ <TSC Offset> [ : <VMCS> [ , <VMCS> ]... ]  ]...
1398 So it is possible to specify different TSC Offsets for different VMCS.
1501 Identify the TSC Offset:
1504  VMCS: 0x103fc6  TSC Offset 0xfffffa6ae070cb20
1505  VMCS: 0x103ff2  TSC Offset 0xfffffa6ae070cb20
1506  VMCS: 0x10fdaa  TSC Offset 0xfffffa6ae070cb20
1507  VMCS: 0x24d57c  TSC Offset 0xfffffa6ae070cb20
1509 Correct Intel PT TSC timestamps for the guest machine: