memory-model/Documentation/explanation.txt

200 	P1 loads from flag before loading from buf, since CPUs execute
211 	execute before itself, the specified outcome is impossible.
261 important assumption that CPUs execute instructions in the same order
829 First, a fence forces the CPU to execute various instructions in
834 	the CPU to execute all po-earlier instructions before any
837 	smp_rmb() forces the CPU to execute all po-earlier loads
840 	smp_wmb() forces the CPU to execute all po-earlier stores
844 	execute the load associated with the fence (e.g., the load
849 	execute all po-earlier instructions before the store
1045 There are many situations where a CPU is obliged to execute two
1053 memory accesses with X ->po Y; then the CPU must execute X before Y if
1079 a store W will force the CPU to execute R before W.  This is very
1094 To be fair about it, all Linux-supported architectures do execute
1111 this situation we know it is possible for the CPU to execute R' before
1113 cannot execute R' before R, because it cannot forward the value before
1138 access the same location), the CPU is obliged to execute W after R.
1187 to ptr does.  And since P1 can't execute its second load
1209 effect of the fence is to cause the CPU not to execute any po-later
1230 share this property: They do not allow the CPU to execute any po-later
1247 execute in a certain order.  hb includes the ppo relation and two
1258 execute before W does.
1263 they execute on different CPUs, and W comes before W' in the coherence
1265 execute before W, because the decision as to which store overwrites
1269 doesn't mean that W has to execute after R.  All that's necessary is
1364 P1 must execute its second load before the first.  Indeed, if the load
1376 Since an instruction can't execute before itself, we are forced to
1418 before P2's load and store execute, P2's smp_store_release()
1424 in the order they execute means that it must not have cycles.  This
1456 And because of the hb links, we know that Z will execute before F.
1463 The existence of a pb link from E to F implies that E must execute
1504 cycle in pb, which is not possible since an instruction cannot execute
1509 they execute means that it cannot have cycles.  This requirement is
1578 execute an smp_mb() fence after the end of the critical section and
1581 synchronize_rcu() routine will execute an smp_mb() fence at its start
1644 before any instruction po-after F can execute.  (However, it does not
1645 imply that E must execute before F; in fact, each synchronize_rcu()
1671 executing and hence before any instruction po-after F can execute.
1697 details; the end result is that E ->rb F implies E must execute
1845 This requires P0 and P2 to execute their loads and stores out of
1899 	that matching calls don't have to execute on the same CPU.
2056 must execute before any instruction po-after the lock-acquire.  This
2085 therefore the load of x must execute before the load of y, even though
2243 5.	they execute concurrently.
2252 which may execute concurrently; if it does then the LKMM says there is
2259 execute concurrently.  The LKMM takes a conservative attitude,
2263 If two memory accesses aren't concurrent then one must execute before
2280 requires not only that X must execute before Y but also that X must
2315 	po-after the barrier can execute.
2344 provides an xb link from Z to Y (i.e., it forces Z to execute before
2388 then execute some of those accesses out of program order, but we
2444 	therefore any loads among those instructions will execute
2448 executes (assuming V does execute), ruling out the possibility of a
2512 *p; the marked load must execute before any of the machine
2614 before the second can execute.  Therefore the two stores cannot be
2719 it is not guaranteed that the load from y will execute after the
2739 for this source code in which W' could execute before R.  Just as with