Lines Matching +full:num +full:- +full:guest +full:- +full:ids
1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v1.0
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
35 1, 0, ecx, 2, dtes64 , 64-bit DS save area
49 1, 0, ecx, 17, pcid , Process-context identifiers
56 1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
61 …1, 0, ecx, 29, f16c , Half-precision floating-point conversion …
63 … 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized sy…
64 1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
65 1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
69 …1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR…
73 1, 0, edx, 9, apic , APIC on-chip
80 1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
90 1, 0, edx, 28, ht , Hyper-threading
92 …1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now r…
96 # Intel cache and TLB information one-byte descriptors
102 2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
107 2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
112 … 2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
117 … 2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
123 4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
124 4, 31:0, eax, 8, cache_self_init , Self-initialializing cache level
125 4, 31:0, eax, 9, fully_associative , Fully-associative cache
128 … 4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
129 4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
130 4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
131 4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
132 … edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
133 … 4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
134 …4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex functi…
139 … 5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
140 … 5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
142 …5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is …
143 …5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using…
144 …5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using…
145 …5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using…
146 …5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using…
147 …5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using…
148 …5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using…
149 …5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using…
150 …5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using…
157 … 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-st…
161 …6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers ar…
183 … 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback struct, 0-based
201 …7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache mo…
204 … 7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcemeent
205 7, 0, ebx, 16, avx512f , AVX-512 foundation instructions
206 … 7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions
210 7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add
214 7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions
215 7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instrs
216 7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instrs
218 …7, 0, ebx, 30, avx512bw , AVX-512 BW (byte/word granular) instructi…
219 …7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extens…
221 … 7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instrs
223 7, 0, ecx, 3, pku , Protection keys for user-space
226 …7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instrs g…
230 … 7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support
232 7, 0, ecx, 12, avx512_bitalg , AVX-512 bit count/shiffle
234 … 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DW/QW
235 …7, 0, ecx, 16, la57 , 57-bit linear addreses (five-level paging)
236 … 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode
239 7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection
245 … 7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages
247 … 7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
248 …7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single prec…
262 7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support
263 7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
264 … 7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support
265 … 7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support
272 7, 1, eax, 4, avx_vnni , AVX-VNNI instructions
273 7, 1, eax, 5, avx512_bf16 , AVX-512 bFloat16 instructions
277 7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB
282 … 7, 1, eax, 19, wrmsrns , WRMSRNS instr (WRMSR-non-serializing)
283 7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations
289 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions
290 7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions
291 …7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from G…
300 7, 2, edx, 6, uclock_disable , UC-lock disable is supported
317 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available
318 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available
322 …0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bit…
342 … 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
344 … 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
345 … 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
346 …x, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)
354 … edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)
369 …0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature…
370 …0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N featu…
372 … 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N feature xsave area is 64-byte ali…
377 … 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based)
378 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported
379 … 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based)
382 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID
393 …1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation
397 …0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supp…
399 …0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one no…
400 … 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported
416 …0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mod…
417 …0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (l…
420 …, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode)
429 …x, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
431 …cx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
432 …, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
433 … 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)
449 …0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mo…
450 …0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT …
451 …0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets …
459 … 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported
489 …3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
490 …3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
491 …:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
492 …1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15)
498 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported
499 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported
500 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported
501 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported
506 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
507 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure
508 … edx, 25:14, tlb_max_addressible_ids, Max num of addressible IDs for logical CPUs sharing thi…
513 …0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction suppo…
514 …0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supp…
515 …0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supp…
547 …0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > …
549 …0x1c, 0, ebx, 0, lbr_cpl , CPL filtering (non-zero IA32_LBR_CTL[2…
550 …0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering (non-zero IA32_LBR_CT…
551 …0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode (IA32_LBR_CTL[3] = 1) …
555 …cx, 19:16, lbr_events_gpc_bmp , LBR PMU-events logging support; bitmap for first 4 GP (ge…
568 # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration
589 # Intel TD (Trust Domain) guest execution environment enumeration
591 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
592 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11
593 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
601 …0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is support…
602 … 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-purpose PMU counters bitmap
607 …0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event supp…
608 …0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event supported
621 0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3
622 0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7
623 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11
629 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3
630 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11
631 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7
643 0x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode
644 0x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No …
658 0x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction
666 0x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter
670 0x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)
671 0x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions
675 0x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR a…
679 0x80000001, 0, edx, 9, apic , APIC on-chip
686 0x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
687 0x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing b…
688 0x80000001, 0, edx, 20, nx , No-execute page protection
692 0x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support
694 0x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
699 # CPU brand ID string, bytes 0 - 15
701 0x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 3
702 0x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 7
703 0x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 11
704 0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15
707 # CPU brand ID string, bytes 16 - 31
709 0x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 19
710 0x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 23
711 0x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 27
712 0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31
715 # CPU brand ID string, bytes 32 - 47
717 0x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 35
718 0x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 39
719 0x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 43
720 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47
777 0x80000007, 0, edx, 7, hw_pstate , Hardware P-state control
780 0x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency int…
791 0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical …
804 0x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred
805 0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred
808 0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segmen…
819 0x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1
821 0x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter si…
843 0x8000000a, 0, edx, 17, gmet , Guest mode execution trap
847 0x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support
853 0x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME addr check
856 # AMD TLB 1G-pages enumeration
870 … 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
872 … 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide
875 # AMD IBS (Instruction-Based Sampling) enumeration
885 0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indicat…
888 0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (…
907 0x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of bits in cache latency coun…
914 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events can be filte…
915 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events can be filte…
931 0x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based)
932 0x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level
933 0x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache
935 0x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-bas…
936 0x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
937 0x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
938 0x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
939 … edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
940 0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level…
946 0x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core un…
947 0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads per core (zero-based)
965 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervi…
968 0x8000001f, 0, eax, 14, debug_swap , SEV-ES: full debug state swap is …
969 0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by th…
973 … eax, 19, virt_ibs , IBS state virtualization is supported for SEV-ES guests
982 … 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum ASID for SEV-enabled SEV-ES-disabled guest
985 # AMD Platform QoS extended feature IDs
992 … 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based)
994 … 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based)
998 0x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes ca…
999 0x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes c…
1000 0x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can …
1001 0x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can…
1008 … 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
1020 0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of microcode patch, in 16-by…
1035 # AMD Secure Multi-key Encryption enumeration
1037 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode is suppor…
1038 0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mode: total num of availa…