Lines Matching +full:1 +full:- +full:7
1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v1.0
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
20 # Leaf 1H
23 1, 0, eax, 3:0, stepping , Stepping ID
24 1, 0, eax, 7:4, base_model , Base CPU model ID
25 1, 0, eax, 11:8, base_family_id , Base CPU family ID
26 1, 0, eax, 13:12, cpu_type , CPU type
27 1, 0, eax, 19:16, ext_model , Extended CPU model ID
28 1, 0, eax, 27:20, ext_family , Extended CPU family ID
29 1, 0, ebx, 7:0, brand_id , Brand index
30 … 1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size
31 1, 0, ebx, 23:16, n_logical_cpu , Logical CPU (HW threads) count
32 1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
33 1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3)
34 1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support
35 1, 0, ecx, 2, dtes64 , 64-bit DS save area
36 1, 0, ecx, 3, monitor , MONITOR/MWAIT support
37 1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store
38 1, 0, ecx, 5, vmx , Virtual Machine Extensions
39 1, 0, ecx, 6, smx , Safer Mode Extensions
40 1, 0, ecx, 7, est , Enhanced Intel SpeedStep
41 1, 0, ecx, 8, tm2 , Thermal Monitor 2
42 1, 0, ecx, 9, ssse3 , Supplemental SSE3
43 1, 0, ecx, 10, cid , L1 Context ID
44 1, 0, ecx, 11, sdbg , Sillicon Debug
45 1, 0, ecx, 12, fma , FMA extensions using YMM state
46 1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support
47 1, 0, ecx, 14, xtpr , xTPR Update Control
48 1, 0, ecx, 15, pdcm , Perfmon and Debug Capability
49 1, 0, ecx, 17, pcid , Process-context identifiers
50 1, 0, ecx, 18, dca , Direct Cache Access
51 1, 0, ecx, 19, sse4_1 , SSE4.1
52 1, 0, ecx, 20, sse4_2 , SSE4.2
53 1, 0, ecx, 21, x2apic , X2APIC support
54 1, 0, ecx, 22, movbe , MOVBE instruction support
55 1, 0, ecx, 23, popcnt , POPCNT instruction support
56 1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
57 1, 0, ecx, 25, aes , AES instructions
58 … 1, 0, ecx, 26, xsave , XSAVE (and related instructions) support
59 …1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enab…
60 1, 0, ecx, 28, avx , AVX instructions support
61 …1, 0, ecx, 29, f16c , Half-precision floating-point conversion …
62 1, 0, ecx, 30, rdrand , RDRAND instruction support
63 …1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtua…
64 1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
65 1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
66 1, 0, edx, 2, de , Debugging Extensions
67 1, 0, edx, 3, pse , Page Size Extension
68 1, 0, edx, 4, tsc , Time Stamp Counter
69 …1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR…
70 1, 0, edx, 6, pae , Physical Address Extensions
71 1, 0, edx, 7, mce , Machine Check Exception
72 1, 0, edx, 8, cx8 , CMPXCHG8B instruction
73 1, 0, edx, 9, apic , APIC on-chip
74 … 1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs
75 1, 0, edx, 12, mtrr , Memory Type Range Registers
76 1, 0, edx, 13, pge , Page Global Extensions
77 1, 0, edx, 14, mca , Machine Check Architecture
78 1, 0, edx, 15, cmov , Conditional Move Instruction
79 1, 0, edx, 16, pat , Page Attribute Table
80 1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
81 1, 0, edx, 18, pn , Processor Serial Number
82 1, 0, edx, 19, clflush , CLFLUSH instruction
83 1, 0, edx, 21, dts , Debug Store
84 1, 0, edx, 22, acpi , Thermal monitor and clock control
85 1, 0, edx, 23, mmx , MMX instructions
86 1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
87 1, 0, edx, 25, sse , SSE instructions
88 1, 0, edx, 26, sse2 , SSE2 instructions
89 1, 0, edx, 27, ss , Self Snoop
90 1, 0, edx, 28, ht , Hyper-threading
91 1, 0, edx, 29, tm , Thermal Monitor
92 …1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now r…
93 1, 0, edx, 31, pbe , Pending Break Enable
96 # Intel cache and TLB information one-byte descriptors
98 …2, 0, eax, 7:0, iteration_count , Number of times this CPUD leaf must be qu…
99 2, 0, eax, 15:8, desc1 , Descriptor #1
102 2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
103 2, 0, ebx, 7:0, desc4 , Descriptor #4
106 2, 0, ebx, 30:24, desc7 , Descriptor #7
107 2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
108 2, 0, ecx, 7:0, desc8 , Descriptor #8
112 … 2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
113 2, 0, edx, 7:0, desc12 , Descriptor #12
117 … 2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
123 4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
124 4, 31:0, eax, 8, cache_self_init , Self-initialializing cache level
125 4, 31:0, eax, 9, fully_associative , Fully-associative cache
128 … 4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
129 4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
130 4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
131 4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
132 … edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
133 … 4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
134 …4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex functi…
139 … 5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
140 … 5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
142 …5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is …
143 …5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using…
144 …5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using…
145 …5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using…
146 …5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using…
147 …5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using…
148 …5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using…
149 …5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using…
150 …5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using…
156 6, 0, eax, 1, turbo_boost , Intel Turbo Boost
157 … 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-st…
161 …6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers ar…
181 … 6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
183 … 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback struct, 0-based
185 # Leaf 7H
188 7, 0, eax, 31:0, leaf7_n_subleaves , Number of cpuid 0x7 subleaves
189 7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support
190 7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported
191 … 7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions)
192 … 7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1
193 7, 0, ebx, 4, hle , Hardware Lock Elision
194 7, 0, ebx, 5, avx2 , AVX2 instruction set
195 …7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exce…
196 … 7, 0, ebx, 7, smep , Supervisor Mode Execution Protection
197 … 7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2
198 7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB
199 …7, 0, ebx, 10, invpcid , INVPCID instruction (Invalidate Processor…
200 … 7, 0, ebx, 11, rtm , Intel restricted transactional memory
201 …7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache mo…
202 … 7, 0, ebx, 13, zero_fcs_fds , Deprecated FPU CS/DS (stored as zero)
203 7, 0, ebx, 14, mpx , Intel memory protection extensions
204 … 7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcemeent
205 7, 0, ebx, 16, avx512f , AVX-512 foundation instructions
206 … 7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions
207 7, 0, ebx, 18, rdseed , RDSEED instruction
208 7, 0, ebx, 19, adx , ADCX/ADOX instructions
209 7, 0, ebx, 20, smap , Supervisor mode access prevention
210 7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add
211 7, 0, ebx, 23, clflushopt , CLFLUSHOPT instruction
212 7, 0, ebx, 24, clwb , CLWB instruction
213 7, 0, ebx, 25, intel_pt , Intel processor trace
214 7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions
215 7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instrs
216 7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instrs
217 7, 0, ebx, 29, sha_ni , SHA/SHA256 instructions
218 …7, 0, ebx, 30, avx512bw , AVX-512 BW (byte/word granular) instructi…
219 …7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extens…
220 7, 0, ecx, 0, prefetchwt1 , PREFETCHWT1 (Intel Xeon Phi only)
221 … 7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instrs
222 7, 0, ecx, 2, umip , User mode instruction protection
223 7, 0, ecx, 3, pku , Protection keys for user-space
224 7, 0, ecx, 4, ospke , OS protection keys enable
225 7, 0, ecx, 5, waitpkg , WAITPKG instructions
226 …7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instrs g…
227 7, 0, ecx, 7, cet_ss , CET shadow stack features
228 7, 0, ecx, 8, gfni , Galois field new instructions
229 7, 0, ecx, 9, vaes , Vector AES instrs
230 … 7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support
231 7, 0, ecx, 11, avx512_vnni , Vector neural network instructions
232 7, 0, ecx, 12, avx512_bitalg , AVX-512 bit count/shiffle
233 7, 0, ecx, 13, tme , Intel total memory encryption
234 … 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DW/QW
235 …7, 0, ecx, 16, la57 , 57-bit linear addreses (five-level paging)
236 … 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode
237 7, 0, ecx, 22, rdpid , RDPID instruction
238 7, 0, ecx, 23, key_locker , Intel key locker support
239 7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection
240 7, 0, ecx, 25, cldemote , CLDEMOTE instruction
241 7, 0, ecx, 27, movdiri , MOVDIRI instruction
242 7, 0, ecx, 28, movdir64b , MOVDIR64B instruction
243 … 7, 0, ecx, 29, enqcmd , Enqueue stores supported (ENQCMD{,S})
244 7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration
245 … 7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages
246 7, 0, edx, 1, sgx_keys , Intel SGX attestation services
247 … 7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
248 …7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single prec…
249 7, 0, edx, 4, fsrm , Fast short REP MOV
250 7, 0, edx, 5, uintr , CPU supports user interrupts
251 7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions
252 7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available
253 7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support
254 … 7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts
255 …7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, suppo…
256 7, 0, edx, 14, serialize , SERIALIZE instruction
257 … 7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part'
258 … 7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking
259 7, 0, edx, 18, pconfig , PCONFIG instruction
260 7, 0, edx, 19, arch_lbr , Intel architectural LBRs
261 7, 0, edx, 20, ibt , CET indirect branch tracking
262 7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support
263 7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
264 … 7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support
265 … 7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support
266 …7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect …
267 … 7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors
268 … 7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR
269 7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR
270 7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR
271 7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable
272 7, 1, eax, 4, avx_vnni , AVX-VNNI instructions
273 7, 1, eax, 5, avx512_bf16 , AVX-512 bFloat16 instructions
274 7, 1, eax, 6, lass , Linear address space separation
275 7, 1, eax, 7, cmpccxadd , CMPccXADD instructions
276 …7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: CPUID leaf 0x23 is suppor…
277 7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB
278 7, 1, eax, 11, fsrs , Fast short REP STOSB
279 7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB
280 …7, 1, eax, 17, fred , FRED: Flexible return and event delivery …
281 7, 1, eax, 18, lkgs , LKGS: Load 'kernel' (userspace) GS
282 … 7, 1, eax, 19, wrmsrns , WRMSRNS instr (WRMSR-non-serializing)
283 7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations
284 7, 1, eax, 22, hreset , History reset support
285 7, 1, eax, 23, avx_ifma , Integer fused multiply add
286 7, 1, eax, 26, lam , Linear address masking
287 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions
288 …7, 1, ebx, 0, intel_ppin , Protected processor inventory number (PPI…
289 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions
290 7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions
291 …7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from G…
292 7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions
293 … 7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use
294 … 7, 2, edx, 0, intel_psfd , Intel predictive store forward disable
295 … 7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
296 … 7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
297 7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
298 7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
299 7, 2, edx, 5, mcdt_no , MCDT mitigation not needed
300 7, 2, edx, 6, uclock_disable , UC-lock disable is supported
310 … 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID
315 … 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available
317 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available
318 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available
321 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available
322 …0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bit…
330 …0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous level…
331 …0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances…
332 0xb, 1:0, ecx, 7:0, domain_nr , This domain level (subleaf ID)
333 0xb, 1:0, ecx, 15:8, domain_type , This domain type
334 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
340 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported
342 … 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
344 … 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
345 … 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
346 …0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-51…
354 … edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)
355 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction
356 0xd, 1, eax, 1, xsavec , XSAVEC instruction
357 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1
358 …0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MS…
359 0xd, 1, eax, 4, xfd , Extended feature disable support
360 …0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS f…
361 0xd, 1, ecx, 8, xss_pt , PT state, supported
362 0xd, 1, ecx, 10, xss_pasid , PASID state, supported
363 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported
364 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported
365 0xd, 1, ecx, 13, xss_hdc , HDC state, supported
366 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported
367 0xd, 1, ecx, 15, xss_lbr , LBR state, supported
368 0xd, 1, ecx, 16, xss_hwp , HWP state, supported
369 …0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature…
370 …0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N featu…
372 …0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N featur…
377 … 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based)
378 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported
379 …0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-…
380 … 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit
381 … 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes
382 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID
383 … 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported
384 …0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring suppo…
385 …0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring suppo…
390 …0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology support…
393 …0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, min…
394 … 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT bitmap of allocation units
395 …0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequ…
396 …0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT CDP (Code and Data Prioritiz…
397 …0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supp…
398 …0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) s…
399 …0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one no…
400 … 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported
408 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions supported
411 … 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 supported
415 …0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: reporting #CP exceptio…
416 …0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mod…
417 …0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (l…
418 …0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES.INIT supported (enclave ini…
419 …0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES.DEBUG supported (enclave pe…
420 …0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclav…
421 …0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES.PROVISIONKEY supported (pro…
422 …0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTES.EINITTOKEN_KEY supported (…
423 …0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES.CET supported (enable CET a…
424 …0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES.KSS supported (Key Separati…
425 …0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES.AEXNOTIFY supported (enclav…
426 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported
427 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported
428 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported
429 …0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported…
430 …0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported …
431 …0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported …
432 …0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) support…
433 …0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supporte…
434 …0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (X…
435 …0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) suppo…
436 …0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) support…
449 …0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mo…
450 …0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT …
451 …0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets …
455 …0x14, 0, ebx, 7, event_trace , Event Trace packet generation through …
458 … 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
459 … 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported
462 …0x14, 1, eax, 2:0, num_address_ranges , Filtering number of configurable Addre…
463 …0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of supported MTC period encodin…
464 …0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of supported Cycle Threshold en…
465 …0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of supported Configurable PSB f…
489 …0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_…
490 …0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_…
491 …0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_…
492 …0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_…
498 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported
499 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported
500 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported
501 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported
506 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
507 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure
508 …25:14, tlb_max_addressible_ids, Max num of addressible IDs for logical CPUs sharing this TLB - 1
513 …0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction suppo…
514 …0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supp…
515 …0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supp…
520 …0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization (KeySource encodin…
522 # Leaf 1AH
528 # Leaf 1BH
536 # Leaf 1CH
540 …0x1c, 0, eax, 1, lbr_depth_16 , Max stack depth (number of LBR entries…
546 …0x1c, 0, eax, 7, lbr_depth_64 , Max stack depth (number of LBR entries…
547 …0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > …
549 … 0, ebx, 0, lbr_cpl , CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported
550 …0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering (non-zero IA32_LBR_CT…
551 …, 0, ebx, 2, lbr_call_stack , Call-stack mode (IA32_LBR_CTL[3] = 1) supp…
553 …0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR …
555 …cx, 19:16, lbr_events_gpc_bmp , LBR PMU-events logging support; bitmap for first 4 GP (ge…
557 # Leaf 1DH
561 … 0x1d, 1, eax, 15:0, amx_palette_size , AMX palette total tiles size, in bytes
562 0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes
563 … 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes
564 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles
565 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows
567 # Leaf 1EH
568 # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration
570 …0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or c…
573 # Leaf 1FH
578 0x1f, 5:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
585 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1
591 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
592 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11
593 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
598 …0x23, 0, eax, 1, subleaf_1_counters , Subleaf 1, PMU counters bitmaps, is va…
601 …0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is support…
602 … 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-purpose PMU counters bitmap
603 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PMU counters bitmap
605 … 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event supported
607 …0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event supp…
608 …0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event supported
611 0x23, 3, eax, 7, td_slots_evt , Topdown slots event supported
621 0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3
622 0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7
623 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11
629 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3
630 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11
631 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7
637 0x80000001, 0, eax, 7:4, e_base_model , Base processor model
643 0x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode
644 0x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No …
650 0x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode
658 0x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction
666 0x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter
670 0x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)
671 0x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions
675 0x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR a…
677 0x80000001, 0, edx, 7, mce , Machine Check Exception
679 0x80000001, 0, edx, 9, apic , APIC on-chip
686 0x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
687 0x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing b…
688 0x80000001, 0, edx, 20, nx , No-execute page protection
692 0x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support
694 0x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
699 # CPU brand ID string, bytes 0 - 15
701 0x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 3
702 0x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 7
703 0x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 11
704 0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15
707 # CPU brand ID string, bytes 16 - 31
709 0x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 19
710 0x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 23
711 0x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 27
712 0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31
715 # CPU brand ID string, bytes 32 - 47
717 0x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 35
718 0x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 39
719 0x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 43
720 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47
725 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entires, 2M and 4M pages
729 0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #entries, 4K pages
733 0x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache line size, in bytes
737 0x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes
753 0x80000006, 0, ecx, 7:0, l2_line_size , L2 cache line size, in bytes
757 0x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes
766 0x80000007, 0, ebx, 1, succor , Software containment of UnCORRect…
771 0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling
777 0x80000007, 0, edx, 7, hw_pstate , Hardware P-state control
780 0x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency int…
789 0x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits
791 0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical …
793 0x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR
804 0x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred
805 0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred
808 0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segmen…
819 0x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1
821 0x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter si…
828 0x8000000a, 0, eax, 7:0, svm_version , SVM revision number
831 0x8000000a, 0, edx, 1, lbrv , LBR virtualization
837 0x8000000a, 0, edx, 7, decodeassists , Decode Assists support
847 0x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support
856 # AMD TLB 1G-pages enumeration
858 0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages
859 0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages
860 0x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #entries, 1G pages
861 0x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB associativity, 1G pages
862 0x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #entries, 1G pages
863 0x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB associativity, 1G pages
864 0x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #entries, 1G pages
865 0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages
870 … 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
871 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
872 … 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide
875 # AMD IBS (Instruction-Based Sampling) enumeration
878 0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling supported
883 … 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits
884 0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication suppor…
885 0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indicat…
888 0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (…
894 0x8000001c, 0, eax, 1, os_lpwval , LWPVAL instruction (EventId=1) is…
903 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Control Block size, in quadwo…
914 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events can be filte…
915 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events can be filte…
917 0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL instruction (EventId=1) is…
931 0x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based)
932 0x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level
933 0x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache
935 0x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-bas…
936 0x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
937 0x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
938 0x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
939 … edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
940 0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level…
946 0x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core un…
947 0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads per core (zero-based)
948 0x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical…
955 0x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization s…
961 0x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadwo stack supp…
965 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervi…
968 0x8000001f, 0, eax, 14, debug_swap , SEV-ES: full debug state swap is …
969 0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by th…
973 … eax, 19, virt_ibs , IBS state virtualization is supported for SEV-ES guests
982 … 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum ASID for SEV-enabled SEV-ES-disabled guest
987 0x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation suppo…
991 0x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size
992 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (…
994 … 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based)
995 0x80000020, 3, ebx, 7:0, bmec_num_events , BMEC number of bandwidth events a…
997 0x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUMA reads can be tracked
998 0x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes ca…
999 0x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes c…
1000 0x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can …
1001 0x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can…
1008 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE i…
1012 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore Ena…
1020 0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of microcode patch, in 16-by…
1026 0x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions …
1035 # AMD Secure Multi-key Encryption enumeration
1037 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode is suppor…
1038 0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mode: total num of availa…
1051 0x80000026, 3:0, ecx, 7:0, domain_level , This domain level (subleaf ID)