Lines Matching full:fetch

29 /* MSR 0xc0011030: IBS Fetch Control */
33 		__u64	fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 			fetch_cnt:16,	/* 16-31: instruction fetch count */
35 			fetch_lat:16,	/* 32-47: instruction fetch latency */
36 			fetch_en:1,	/* 48: instruction fetch enable */
37 			fetch_val:1,	/* 49: instruction fetch valid */
38 			fetch_comp:1,	/* 50: instruction fetch complete */
43 			l1tlb_miss:1,	/* 55: i-cache fetch missed in L1TLB */
44 			l2tlb_miss:1,	/* 56: i-cache fetch missed in L2TLB */
46 			fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
49 			fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
50 			fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
132 /* MSR 0xc001103c: IBS Fetch Control Extended */
136 		__u64	itlb_refill_lat:16,	/* 0-15: ITLB Refill latency for sampled fetch */