include/asm/csr.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
38 #define SR_FS_VS	(SR_FS | SR_VS) /* Vector and Floating-Point Unit */
47 #define SR_UXL		_AC(0x300000000, UL) /* XLEN mask for U-mode */
48 #define SR_UXL_32	_AC(0x100000000, UL) /* XLEN = 32 for U-mode */
49 #define SR_UXL_64	_AC(0x200000000, UL) /* XLEN = 64 for U-mode */
71 /* Exception cause high bit - is an interrupt if set */
72 #define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
75 #define IRQ_S_SOFT		1
86 #define IRQ_LOCAL_MAX		(IRQ_PMU_OVF + 1)
87 #define IRQ_LOCAL_MASK		GENMASK((IRQ_LOCAL_MAX - 1), 0)
91 #define EXC_INST_ACCESS		1
137 #define HGATP_MODE_SV32X4	_AC(1, UL)
167 #define VSIP_TO_HVIP_SHIFT	(IRQ_VS_SOFT - IRQ_S_SOFT)
168 #define VSIP_VALID_MASK		((_AC(1, UL) << IRQ_S_SOFT) | \
169 				 (_AC(1, UL) << IRQ_S_TIMER) | \
170 				 (_AC(1, UL) << IRQ_S_EXT))
194 #define ENVCFG_STCE			(_AC(1, ULL) << 63)
195 #define ENVCFG_PBMTE			(_AC(1, ULL) << 62)
196 #define ENVCFG_CBZE			(_AC(1, UL) << 7)
197 #define ENVCFG_CBCFE			(_AC(1, UL) << 6)
207 #define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
209 #define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
211 #define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
213 #define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
215 #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
301 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
305 /* Supervisor-Level Interrupts (AIA) */
309 /* Supervisor-Level High-Half CSRs (AIA) */
342 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
348 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
352 /* VS-Level Interrupts (H-extension with AIA) */
356 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
388 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
392 /* Machine-Level Interrupts (AIA) */
400 /* Machine-Level High-Half CSRs (AIA) */
482 	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
508 	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
525 	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\