Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/gpr-num.h>
21 * [20-19] : Op0
22 * [18-16] : Op1
23 * [15-12] : CRn
24 * [11-8] : CRm
25 * [7-5] : Op2
31 #define CRn_shift 12
82 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
132 #include "asm/sysreg-defs.h"
149 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
151 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
152 #define OSLSR_EL1_OSLK BIT(1)
212 #define SYS_PAR_EL1_F BIT(0)
246 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
247 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
249 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
250 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
251 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
252 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
253 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
258 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
263 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
264 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
265 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
266 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
267 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
268 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
269 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
270 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
271 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
272 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
273 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
274 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
275 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
284 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
285 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
286 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
287 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
288 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
289 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
290 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
291 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
320 * n: 0-15
326 * n: 0-15
331 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
405 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
406 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
407 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
408 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
409 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
415 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
421 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
422 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
423 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
424 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
425 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
426 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
427 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
428 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
430 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
440 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
469 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
481 #define SCTLR_ELx_ENTP2 (BIT(60))
482 #define SCTLR_ELx_DSSBS (BIT(44))
483 #define SCTLR_ELx_ATA (BIT(43))
488 #define SCTLR_ELx_ITFSB (BIT(37))
489 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
490 #define SCTLR_ELx_ENIB (BIT(30))
491 #define SCTLR_ELx_LSMAOE (BIT(29))
492 #define SCTLR_ELx_nTLSMD (BIT(28))
493 #define SCTLR_ELx_ENDA (BIT(27))
494 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
495 #define SCTLR_ELx_EIS (BIT(22))
496 #define SCTLR_ELx_IESB (BIT(21))
497 #define SCTLR_ELx_TSCXT (BIT(20))
498 #define SCTLR_ELx_WXN (BIT(19))
499 #define SCTLR_ELx_ENDB (BIT(13))
500 #define SCTLR_ELx_I (BIT(12))
501 #define SCTLR_ELx_EOS (BIT(11))
502 #define SCTLR_ELx_SA (BIT(3))
503 #define SCTLR_ELx_C (BIT(2))
504 #define SCTLR_ELx_A (BIT(1))
505 #define SCTLR_ELx_M (BIT(0))
508 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
509 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
510 (BIT(29)))
512 #define SCTLR_EL2_BT (BIT(36))
600 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
601 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
603 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
604 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
606 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
607 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
610 #define SYS_GCR_EL1_RRND (BIT(16))
620 /* TFSR{,E0}_EL1 bit definitions */
627 #define SYS_MPIDR_SAFE_VAL (BIT(31))
634 #define TRFCR_EL2_CX BIT(3)
635 #define TRFCR_ELx_ExTRE BIT(1)
636 #define TRFCR_ELx_E0TRE BIT(0)
639 /* ICH_MISR_EL2 bit definitions */
643 /* ICH_LR*_EL2 bit definitions */
644 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
657 /* ICH_HCR_EL2 bit definitions */
663 #define ICH_HCR_TALL1 (1 << 12)
668 /* ICH_VMCR_EL2 bit definitions */
688 /* ICH_VTR_EL2 bit definitions */
806 * set mask are set. Other bits are left as-is.