Lines Matching +full:0 +full:x0000fc00
32 #define MSP_BIG_ENDIAN 0x00000000
33 #define MSP_LITTLE_ENDIAN 0x00001000
34 #define MSP_UNEXPECTED_FS_ABORT 0x00000000
35 #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
36 #define MSP_NON_MODE_BIT_MASK 0x00009000
39 #define RX_ENABLE 0x00000001
40 #define RX_FIFO_ENABLE 0x00000002
41 #define RX_SYNC_SRG 0x00000010
42 #define RX_CLK_POL_RISING 0x00000020
43 #define RX_CLK_SEL_SRG 0x00000040
44 #define TX_ENABLE 0x00000100
45 #define TX_FIFO_ENABLE 0x00000200
46 #define TX_SYNC_SRG_PROG 0x00001800
47 #define TX_SYNC_SRG_AUTO 0x00001000
48 #define TX_CLK_POL_RISING 0x00002000
49 #define TX_CLK_SEL_SRG 0x00004000
50 #define TX_EXTRA_DELAY_ENABLE 0x00008000
51 #define SRG_ENABLE 0x00010000
52 #define FRAME_GEN_ENABLE 0x00100000
53 #define SRG_CLK_SEL_APB 0x00000000
54 #define RX_FIFO_SYNC_HI 0x00000000
55 #define TX_FIFO_SYNC_HI 0x00000000
56 #define SPI_CLK_MODE_NORMAL 0x00000000
60 #define MSP_DR 0x00
61 #define MSP_GCR 0x04
62 #define MSP_TCF 0x08
63 #define MSP_RCF 0x0c
64 #define MSP_SRG 0x10
65 #define MSP_FLR 0x14
66 #define MSP_DMACR 0x18
68 #define MSP_IMSC 0x20
69 #define MSP_RIS 0x24
70 #define MSP_MIS 0x28
71 #define MSP_ICR 0x2c
72 #define MSP_MCR 0x30
73 #define MSP_RCV 0x34
74 #define MSP_RCM 0x38
76 #define MSP_TCE0 0x40
77 #define MSP_TCE1 0x44
78 #define MSP_TCE2 0x48
79 #define MSP_TCE3 0x4c
81 #define MSP_RCE0 0x60
82 #define MSP_RCE1 0x64
83 #define MSP_RCE2 0x68
84 #define MSP_RCE3 0x6c
85 #define MSP_IODLY 0x70
87 #define MSP_ITCR 0x80
88 #define MSP_ITIP 0x84
89 #define MSP_ITOP 0x88
90 #define MSP_TSTDR 0x8c
92 #define MSP_PID0 0xfe0
93 #define MSP_PID1 0xfe4
94 #define MSP_PID2 0xfe8
95 #define MSP_PID3 0xfec
97 #define MSP_CID0 0xff0
98 #define MSP_CID1 0xff4
99 #define MSP_CID2 0xff8
100 #define MSP_CID3 0xffc
103 #define RX_ENABLE_MASK BIT(0)
126 #define RXEN_SHIFT 0
148 #define RCKPOL_MASK BIT(0)
149 #define TCKPOL_MASK BIT(0)
150 #define SPICKM_MASK (BIT(1) | BIT(0))
154 #define P1ELEN_SHIFT 0
166 #define P1ELEN_MASK 0x00000007
167 #define P2ELEN_MASK 0x00070000
168 #define P1FLEN_MASK 0x00000378
169 #define P2FLEN_MASK 0x03780000
170 #define DDLY_MASK 0x00003000
171 #define DTYP_MASK 0x00000600
172 #define P2SM_MASK 0x04000000
173 #define P2EN_MASK 0x08000000
174 #define ENDN_MASK 0x00001000
175 #define TFSPOL_MASK 0x00000400
176 #define TBSWAP_MASK 0x30000000
177 #define COMPANDING_MODE_MASK 0x00000c00
178 #define FSYNC_MASK 0x00008000
196 #define RX_BUSY BIT(0)
203 #define RBUSY_SHIFT 0
211 #define RMCEN_SHIFT 0
218 #define SCKDIV_SHIFT 0
222 #define SCK_DIV_MASK 0x0000003FF
223 #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00)
224 #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000)
227 #define RX_DMA_ENABLE BIT(0)
230 #define RDMAE_SHIFT 0
234 #define RX_SERVICE_INT BIT(0)
242 #define ALL_INT 0x000000ff
245 #define MSP_ITCR_ITEN BIT(0)
248 #define RMCEN_BIT 0
262 MSP_FRAME_LEN_1 = 0,
276 MSP_ELEM_LEN_8 = 0,
293 MSP_FSYNC_UNIGNORE = 0,
303 MSP_BTF_MS_BIT_FIRST = 0,
308 MSP_FSYNC_POL_ACT_HI = 0,
314 MSP_DELAY_0 = 0,
322 MSP_FALLING_EDGE = 0,
327 MSP_SWAP_NONE = 0,
334 MSP_COMPRESS_MODE_LINEAR = 0,
340 MSP_EXPAND_MODE_LINEAR = 0,
364 MSP_DIR_TX = 0x01,
365 MSP_DIR_RX = 0x02,
370 MSP_DATA_BITS_8 = 0x00,
381 MSP_STATE_IDLE = 0,
387 MSP_COMPARISON_DISABLED = 0,