Lines Matching refs:writel
138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
262 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
292 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel()
295 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
297 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
299 writel(mcfg->tx_channel_2_enable, in configure_multichannel()
301 writel(mcfg->tx_channel_3_enable, in configure_multichannel()
313 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? in configure_multichannel()
316 writel(mcfg->rx_channel_0_enable, in configure_multichannel()
318 writel(mcfg->rx_channel_1_enable, in configure_multichannel()
320 writel(mcfg->rx_channel_2_enable, in configure_multichannel()
322 writel(mcfg->rx_channel_3_enable, in configure_multichannel()
332 writel(reg_val_MCR | in configure_multichannel()
336 writel(mcfg->comparison_mask, in configure_multichannel()
338 writel(mcfg->comparison_value, in configure_multichannel()
368 writel(reg_val_DMACR, msp->registers + MSP_DMACR); in enable_msp()
370 writel(config->iodelay, msp->registers + MSP_IODLY); in enable_msp()
374 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); in enable_msp()
385 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_rx()
393 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_rx()
402 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_tx()
403 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); in flush_fifo_tx()
410 writel(0x0, msp->registers + MSP_ITCR); in flush_fifo_tx()
411 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_tx()
465 writel(new_reg, msp->registers + MSP_GCR); in ux500_msp_i2s_open()
489 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); in disable_msp_rx()
491 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_rx()
493 writel(reg_val_IMSC & in disable_msp_rx()
505 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); in disable_msp_tx()
507 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_tx()
509 writel(reg_val_IMSC & in disable_msp_tx()
526 writel(reg_val_GCR | LOOPBACK_MASK, in disable_msp()
533 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
540 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
573 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
601 writel((readl(msp->registers + MSP_GCR) & in ux500_msp_i2s_close()
605 writel(0, msp->registers + MSP_GCR); in ux500_msp_i2s_close()
606 writel(0, msp->registers + MSP_TCF); in ux500_msp_i2s_close()
607 writel(0, msp->registers + MSP_RCF); in ux500_msp_i2s_close()
608 writel(0, msp->registers + MSP_DMACR); in ux500_msp_i2s_close()
609 writel(0, msp->registers + MSP_SRG); in ux500_msp_i2s_close()
610 writel(0, msp->registers + MSP_MCR); in ux500_msp_i2s_close()
611 writel(0, msp->registers + MSP_RCM); in ux500_msp_i2s_close()
612 writel(0, msp->registers + MSP_RCV); in ux500_msp_i2s_close()
613 writel(0, msp->registers + MSP_TCE0); in ux500_msp_i2s_close()
614 writel(0, msp->registers + MSP_TCE1); in ux500_msp_i2s_close()
615 writel(0, msp->registers + MSP_TCE2); in ux500_msp_i2s_close()
616 writel(0, msp->registers + MSP_TCE3); in ux500_msp_i2s_close()
617 writel(0, msp->registers + MSP_RCE0); in ux500_msp_i2s_close()
618 writel(0, msp->registers + MSP_RCE1); in ux500_msp_i2s_close()
619 writel(0, msp->registers + MSP_RCE2); in ux500_msp_i2s_close()
620 writel(0, msp->registers + MSP_RCE3); in ux500_msp_i2s_close()