Lines Matching +full:tegra210 +full:- +full:ahub
1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_peq.c - Tegra210 PEQ driver
31 1495012349, /* Pre-gain */
34 536870912, -1073741824, 536870912, 2143508246, -1069773768, /* Band-0 */
35 134217728, -265414508, 131766272, 2140402222, -1071252997, /* Band-1 */
36 268435456, -233515765, -33935948, 1839817267, -773826124, /* Band-2 */
37 536870912, -672537913, 139851540, 1886437554, -824433167, /* Band-3 */
38 268435456, -114439279, 173723964, 205743566, 278809729, /* Band-4 */
39 1, 0, 0, 0, 0, /* Band-5 */
40 1, 0, 0, 0, 0, /* Band-6 */
41 1, 0, 0, 0, 0, /* Band-7 */
42 1, 0, 0, 0, 0, /* Band-8 */
43 1, 0, 0, 0, 0, /* Band-9 */
44 1, 0, 0, 0, 0, /* Band-10 */
45 1, 0, 0, 0, 0, /* Band-11 */
47 963423114, /* Post-gain */
51 23, /* Pre-shift */
53 28, /* Post-shift */
73 * Since all ahub non-io modules work under same ahub clock it is not in tegra210_peq_read_ram()
74 * necessary to check ahub read busy bit after every read. in tegra210_peq_read_ram()
102 (struct soc_mixer_control *)kcontrol->private_value; in tegra210_peq_get()
105 unsigned int mask = (1 << fls(mc->max)) - 1; in tegra210_peq_get()
108 regmap_read(ope->peq_regmap, mc->reg, &val); in tegra210_peq_get()
110 ucontrol->value.integer.value[0] = (val >> mc->shift) & mask; in tegra210_peq_get()
112 if (!mc->invert) in tegra210_peq_get()
115 ucontrol->value.integer.value[0] = in tegra210_peq_get()
116 mc->max - ucontrol->value.integer.value[0]; in tegra210_peq_get()
125 (struct soc_mixer_control *)kcontrol->private_value; in tegra210_peq_put()
128 unsigned int mask = (1 << fls(mc->max)) - 1; in tegra210_peq_put()
132 val = (ucontrol->value.integer.value[0] & mask); in tegra210_peq_put()
134 if (mc->invert) in tegra210_peq_put()
135 val = mc->max - val; in tegra210_peq_put()
137 val = val << mc->shift; in tegra210_peq_put()
139 regmap_update_bits_check(ope->peq_regmap, mc->reg, (mask << mc->shift), in tegra210_peq_put()
148 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_peq_ram_get()
151 u32 i, reg_ctrl = params->soc.base; in tegra210_peq_ram_get()
152 u32 reg_data = reg_ctrl + cmpnt->val_bytes; in tegra210_peq_ram_get()
155 pm_runtime_get_sync(cmpnt->dev); in tegra210_peq_ram_get()
157 tegra210_peq_read_ram(ope->peq_regmap, reg_ctrl, reg_data, in tegra210_peq_ram_get()
158 params->shift, data, params->soc.num_regs); in tegra210_peq_ram_get()
160 pm_runtime_put_sync(cmpnt->dev); in tegra210_peq_ram_get()
162 for (i = 0; i < params->soc.num_regs; i++) in tegra210_peq_ram_get()
163 ucontrol->value.integer.value[i] = (long)data[i]; in tegra210_peq_ram_get()
171 struct tegra_soc_bytes *params = (void *)kcontrol->private_value; in tegra210_peq_ram_put()
174 u32 i, reg_ctrl = params->soc.base; in tegra210_peq_ram_put()
175 u32 reg_data = reg_ctrl + cmpnt->val_bytes; in tegra210_peq_ram_put()
178 for (i = 0; i < params->soc.num_regs; i++) in tegra210_peq_ram_put()
179 data[i] = (s32)ucontrol->value.integer.value[i]; in tegra210_peq_ram_put()
181 pm_runtime_get_sync(cmpnt->dev); in tegra210_peq_ram_put()
183 tegra210_peq_write_ram(ope->peq_regmap, reg_ctrl, reg_data, in tegra210_peq_ram_put()
184 params->shift, data, params->soc.num_regs); in tegra210_peq_ram_put()
186 pm_runtime_put_sync(cmpnt->dev); in tegra210_peq_ram_put()
194 struct soc_bytes *params = (void *)kcontrol->private_value; in tegra210_peq_param_info()
196 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in tegra210_peq_param_info()
197 uinfo->value.integer.min = INT_MIN; in tegra210_peq_param_info()
198 uinfo->value.integer.max = INT_MAX; in tegra210_peq_param_info()
199 uinfo->count = params->num_regs; in tegra210_peq_param_info()
205 TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " Biquad Gain Params", \
213 TEGRA_SOC_BYTES_EXT("PEQ Channel-" #chan " Biquad Shift Params", \
227 TEGRA210_PEQ_MAX_BIQUAD_STAGES - 1, 0,
361 pm_runtime_get_sync(cmpnt->dev); in tegra210_peq_component_init()
362 regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CFG, in tegra210_peq_component_init()
365 regmap_update_bits(ope->peq_regmap, TEGRA210_PEQ_CFG, in tegra210_peq_component_init()
367 (TEGRA210_PEQ_BIQUAD_INIT_STAGE - 1) << in tegra210_peq_component_init()
370 /* Initialize PEQ AHUB RAM with default params */ in tegra210_peq_component_init()
374 tegra210_peq_write_ram(ope->peq_regmap, in tegra210_peq_component_init()
382 tegra210_peq_write_ram(ope->peq_regmap, in tegra210_peq_component_init()
391 pm_runtime_put_sync(cmpnt->dev); in tegra210_peq_component_init()
401 struct device *dev = &pdev->dev; in tegra210_peq_regmap_init()
408 child = of_get_child_by_name(dev->of_node, "equalizer"); in tegra210_peq_regmap_init()
410 return -ENODEV; in tegra210_peq_regmap_init()
423 ope->peq_regmap = devm_regmap_init_mmio(dev, regs, in tegra210_peq_regmap_init()
425 if (IS_ERR(ope->peq_regmap)) { in tegra210_peq_regmap_init()
427 return PTR_ERR(ope->peq_regmap); in tegra210_peq_regmap_init()
430 regcache_cache_only(ope->peq_regmap, true); in tegra210_peq_regmap_init()