Lines Matching full:mbdrc

3 // tegra210_mbdrc.c - Tegra210 MBDRC driver
52 /* Default MBDRC parameters */
534 	SOC_ENUM_EXT("MBDRC Peak RMS Mode", tegra210_mbdrc_peak_rms_enum,
537 	SOC_ENUM_EXT("MBDRC Filter Structure",
541 	SOC_ENUM_EXT("MBDRC Frame Size", tegra210_mbdrc_frame_size_enum,
544 	SOC_ENUM_EXT("MBDRC Mode", tegra210_mbdrc_mode_enum,
547 	SOC_SINGLE_EXT("MBDRC RMS Offset", TEGRA210_MBDRC_CFG,
551 	SOC_SINGLE_EXT("MBDRC Shift Control", TEGRA210_MBDRC_CFG,
555 	SOC_SINGLE_EXT("MBDRC Fast Attack Factor", TEGRA210_MBDRC_FAST_FACTOR,
559 	SOC_SINGLE_EXT("MBDRC Fast Release Factor", TEGRA210_MBDRC_FAST_FACTOR,
563 	SOC_SINGLE_RANGE_EXT_TLV("MBDRC Master Volume",
570 	TEGRA_SOC_BYTES_EXT("MBDRC IIR Stages", TEGRA210_MBDRC_IIR_CFG,
578 	TEGRA_SOC_BYTES_EXT("MBDRC In Attack Time Const", TEGRA210_MBDRC_IN_ATTACK,
586 	TEGRA_SOC_BYTES_EXT("MBDRC In Release Time Const", TEGRA210_MBDRC_IN_RELEASE,
594 	TEGRA_SOC_BYTES_EXT("MBDRC Fast Attack Time Const", TEGRA210_MBDRC_FAST_ATTACK,
602 	TEGRA_SOC_BYTES_EXT("MBDRC In Threshold", TEGRA210_MBDRC_IN_THRESHOLD,
608 	TEGRA_SOC_BYTES_EXT("MBDRC Out Threshold", TEGRA210_MBDRC_OUT_THRESHOLD,
614 	TEGRA_SOC_BYTES_EXT("MBDRC Ratio", TEGRA210_MBDRC_RATIO_1ST,
621 	TEGRA_SOC_BYTES_EXT("MBDRC Makeup Gain", TEGRA210_MBDRC_MAKEUP_GAIN,
629 	TEGRA_SOC_BYTES_EXT("MBDRC Init Gain", TEGRA210_MBDRC_INIT_GAIN,
637 	TEGRA_SOC_BYTES_EXT("MBDRC Attack Gain", TEGRA210_MBDRC_GAIN_ATTACK,
645 	TEGRA_SOC_BYTES_EXT("MBDRC Release Gain", TEGRA210_MBDRC_GAIN_RELEASE,
653 	TEGRA_SOC_BYTES_EXT("MBDRC Fast Release Gain",
662 	TEGRA_SOC_BYTES_EXT("MBDRC Low Band Biquad Coeffs",
669 	TEGRA_SOC_BYTES_EXT("MBDRC Mid Band Biquad Coeffs",
677 	TEGRA_SOC_BYTES_EXT("MBDRC High Band Biquad Coeffs",
755 	.name			= "mbdrc",
807 	/* Initialize MBDRC registers and AHUB RAM with default params */  in tegra210_mbdrc_component_init()
995 		dev_err(dev, "fail to get MBDRC resource\n");  in tegra210_mbdrc_regmap_init()