Lines Matching +full:tx1 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_ahub.c - Tegra210 AHUB driver
5 // Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved.
22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; in tegra_ahub_get_value_enum()
23 unsigned int reg, i, bit_pos = 0; in tegra_ahub_get_value_enum()
27 * If nothing is set, position would be 0 and it corresponds to 'None'. in tegra_ahub_get_value_enum()
29 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_get_value_enum()
32 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); in tegra_ahub_get_value_enum()
34 reg_val &= ahub->soc_data->mask[i]; in tegra_ahub_get_value_enum()
38 (8 * cmpnt->val_bytes * i); in tegra_ahub_get_value_enum()
44 for (i = 0; i < e->items; i++) { in tegra_ahub_get_value_enum()
45 if (bit_pos == e->values[i]) { in tegra_ahub_get_value_enum()
46 uctl->value.enumerated.item[0] = i; in tegra_ahub_get_value_enum()
51 return 0; in tegra_ahub_get_value_enum()
60 struct soc_enum *e = (struct soc_enum *)kctl->private_value; in tegra_ahub_put_value_enum()
62 unsigned int *item = uctl->value.enumerated.item; in tegra_ahub_put_value_enum()
63 unsigned int value = e->values[item[0]]; in tegra_ahub_put_value_enum()
64 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; in tegra_ahub_put_value_enum()
65 int change = 0; in tegra_ahub_put_value_enum()
67 if (item[0] >= e->items) in tegra_ahub_put_value_enum()
68 return -EINVAL; in tegra_ahub_put_value_enum()
72 reg_idx = (value - 1) / (8 * cmpnt->val_bytes); in tegra_ahub_put_value_enum()
73 bit_pos = (value - 1) % (8 * cmpnt->val_bytes); in tegra_ahub_put_value_enum()
82 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_put_value_enum()
83 update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); in tegra_ahub_put_value_enum()
84 update[i].val = (i == reg_idx) ? reg_val : 0; in tegra_ahub_put_value_enum()
85 update[i].mask = ahub->soc_data->mask[i]; in tegra_ahub_put_value_enum()
93 item[0], e, in tegra_ahub_put_value_enum()
111 /* XBAR <-> I2S <-> Codec */
117 /* XBAR <- DMIC <- Codec */
121 /* XBAR -> SFC -> XBAR */
130 /* XBAR -> MVC -> XBAR */
135 /* XBAR -> AMX(4:1) -> XBAR */
146 /* XBAR -> ADX(1:4) -> XBAR */
148 DAI(ADX1 TX1),
153 DAI(ADX2 TX1),
157 /* XBAR -> MIXER(10:5) -> XBAR */
168 DAI(MIXER1 TX1),
173 /* XBAR -> OPE -> XBAR */
201 /* XBAR <-> I2S <-> Codec */
208 /* XBAR <- DMIC <- Codec */
213 /* XBAR -> DSPK -> Codec */
216 /* XBAR -> SFC -> XBAR */
225 /* XBAR -> MVC -> XBAR */
230 /* XBAR -> AMX(4:1) -> XBAR */
251 /* XBAR -> ADX(1:4) -> XBAR */
253 DAI(ADX1 TX1),
258 DAI(ADX2 TX1),
263 DAI(ADX3 TX1),
268 DAI(ADX4 TX1),
272 /* XBAR -> MIXER1(10:5) -> XBAR */
283 DAI(MIXER1 TX1),
288 /* XBAR -> ASRC -> XBAR */
290 DAI(ASRC1 TX1),
302 /* XBAR -> OPE -> XBAR */
335 "ADX1 TX1",
339 "ADX2 TX1",
343 "MIXER1 TX1",
394 "ADX1 TX1",
398 "ADX2 TX1",
402 "ADX3 TX1",
406 "ADX4 TX1",
410 "MIXER1 TX1",
415 "ASRC1 TX1",
425 0,
427 MUX_VALUE(0, 0),
428 MUX_VALUE(0, 1),
429 MUX_VALUE(0, 2),
430 MUX_VALUE(0, 3),
431 MUX_VALUE(0, 4),
432 MUX_VALUE(0, 5),
433 MUX_VALUE(0, 6),
434 MUX_VALUE(0, 7),
435 MUX_VALUE(0, 8),
436 MUX_VALUE(0, 9),
438 MUX_VALUE(0, 16),
439 MUX_VALUE(0, 17),
440 MUX_VALUE(0, 18),
441 MUX_VALUE(0, 19),
442 MUX_VALUE(0, 20),
448 MUX_VALUE(0, 24),
449 MUX_VALUE(0, 25),
450 MUX_VALUE(0, 26),
451 MUX_VALUE(0, 27),
468 MUX_VALUE(1, 0),
474 MUX_VALUE(2, 0),
479 0,
481 MUX_VALUE(0, 0),
482 MUX_VALUE(0, 1),
483 MUX_VALUE(0, 2),
484 MUX_VALUE(0, 3),
485 MUX_VALUE(0, 4),
486 MUX_VALUE(0, 5),
487 MUX_VALUE(0, 6),
488 MUX_VALUE(0, 7),
489 MUX_VALUE(0, 8),
490 MUX_VALUE(0, 9),
491 MUX_VALUE(0, 10),
492 MUX_VALUE(0, 11),
493 MUX_VALUE(0, 12),
494 MUX_VALUE(0, 13),
495 MUX_VALUE(0, 14),
496 MUX_VALUE(0, 15),
498 MUX_VALUE(0, 16),
499 MUX_VALUE(0, 17),
500 MUX_VALUE(0, 18),
501 MUX_VALUE(0, 19),
502 MUX_VALUE(0, 20),
503 MUX_VALUE(0, 21),
515 MUX_VALUE(0, 24),
516 MUX_VALUE(0, 25),
517 MUX_VALUE(0, 26),
518 MUX_VALUE(0, 27),
536 MUX_VALUE(3, 0),
545 MUX_VALUE(1, 0),
558 MUX_VALUE(2, 0),
562 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00);
563 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01);
564 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02);
565 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03);
566 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04);
567 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05);
568 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06);
569 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07);
570 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08);
571 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09);
572 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10);
573 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
574 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
575 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
576 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
577 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18);
578 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19);
579 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a);
580 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b);
581 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48);
582 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49);
583 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50);
584 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51);
585 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52);
586 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53);
587 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54);
588 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55);
589 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56);
590 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57);
591 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58);
592 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59);
593 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20);
594 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21);
595 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22);
596 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23);
597 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24);
598 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25);
599 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26);
600 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27);
601 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28);
602 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29);
603 MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40);
604 MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41);
607 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
608 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01);
609 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02);
610 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03);
611 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04);
612 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05);
613 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06);
614 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07);
615 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08);
616 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09);
617 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10);
618 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11);
619 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12);
620 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13);
621 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14);
622 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a);
623 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b);
624 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c);
625 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d);
626 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e);
627 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f);
628 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15);
629 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30);
630 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31);
631 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
632 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
633 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
634 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
635 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18);
636 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19);
637 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a);
638 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b);
639 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48);
640 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49);
641 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50);
642 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51);
643 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52);
644 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53);
645 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54);
646 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55);
647 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56);
648 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57);
649 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58);
650 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59);
651 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a);
652 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b);
653 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64);
654 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65);
655 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66);
656 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67);
657 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60);
658 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61);
659 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62);
660 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63);
661 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20);
662 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21);
663 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22);
664 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23);
665 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24);
666 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25);
667 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26);
668 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27);
669 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28);
670 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29);
671 MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c);
672 MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d);
673 MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e);
674 MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f);
675 MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70);
676 MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71);
677 MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72);
678 MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40);
681 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44);
682 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45);
683 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48);
684 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49);
685 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a);
686 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b);
687 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c);
688 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d);
689 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e);
690 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f);
691 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50);
692 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51);
693 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52);
694 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53);
695 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58);
696 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59);
697 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a);
698 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b);
699 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c);
700 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d);
701 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e);
702 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f);
703 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60);
704 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61);
705 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62);
706 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63);
707 MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64);
708 MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65);
709 MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66);
710 MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67);
711 MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68);
712 MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69);
713 MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a);
752 TX_WIDGETS("ADX1 TX1"),
756 TX_WIDGETS("ADX2 TX1"),
770 TX_WIDGETS("MIXER1 TX1"),
842 TX_WIDGETS("ADX1 TX1"),
846 TX_WIDGETS("ADX2 TX1"),
850 TX_WIDGETS("ADX3 TX1"),
854 TX_WIDGETS("ADX4 TX1"),
868 TX_WIDGETS("MIXER1 TX1"),
880 TX_WIDGETS("ASRC1 TX1"),
952 TX_WIDGETS("ADX1 TX1"),
956 TX_WIDGETS("ADX2 TX1"),
960 TX_WIDGETS("ADX3 TX1"),
964 TX_WIDGETS("ADX4 TX1"),
978 TX_WIDGETS("MIXER1 TX1"),
990 TX_WIDGETS("ASRC1 TX1"),
1000 { name " XBAR-TX", NULL, name " Mux" }, \
1001 { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \
1002 { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \
1003 { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \
1004 { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \
1005 { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \
1006 { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \
1007 { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \
1008 { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \
1009 { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \
1010 { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \
1011 { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \
1012 { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \
1013 { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \
1014 { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \
1015 { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \
1016 { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \
1017 { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \
1018 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \
1019 { name " Mux", "SFC1", "SFC1 XBAR-RX" }, \
1020 { name " Mux", "SFC2", "SFC2 XBAR-RX" }, \
1021 { name " Mux", "SFC3", "SFC3 XBAR-RX" }, \
1022 { name " Mux", "SFC4", "SFC4 XBAR-RX" }, \
1023 { name " Mux", "MVC1", "MVC1 XBAR-RX" }, \
1024 { name " Mux", "MVC2", "MVC2 XBAR-RX" }, \
1025 { name " Mux", "AMX1", "AMX1 XBAR-RX" }, \
1026 { name " Mux", "AMX2", "AMX2 XBAR-RX" }, \
1027 { name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \
1028 { name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \
1029 { name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \
1030 { name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \
1031 { name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \
1032 { name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \
1033 { name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \
1034 { name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \
1035 { name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \
1036 { name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \
1037 { name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \
1038 { name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \
1039 { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, \
1040 { name " Mux", "OPE1", "OPE1 XBAR-RX" },
1043 { name " Mux", "OPE2", "OPE2 XBAR-RX" },
1046 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \
1047 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \
1048 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \
1049 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \
1050 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \
1051 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \
1052 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \
1053 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \
1054 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \
1055 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \
1056 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \
1057 { name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \
1058 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \
1059 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \
1060 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \
1061 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \
1062 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \
1063 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \
1064 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \
1065 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \
1066 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \
1067 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \
1068 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \
1069 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \
1070 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \
1071 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \
1072 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \
1073 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" },
1085 { name " XBAR-Playback", NULL, name " Playback" }, \
1086 { name " XBAR-RX", NULL, name " XBAR-Playback"}, \
1087 { name " XBAR-Capture", NULL, name " XBAR-TX" }, \
1088 { name " Capture", NULL, name " XBAR-Capture" },
1283 .mask[0] = TEGRA210_XBAR_REG_MASK_0,
1295 .mask[0] = TEGRA186_XBAR_REG_MASK_0,
1307 .mask[0] = TEGRA186_XBAR_REG_MASK_0,
1315 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
1316 { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
1317 { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 },
1326 regcache_cache_only(ahub->regmap, true); in tegra_ahub_runtime_suspend()
1327 regcache_mark_dirty(ahub->regmap); in tegra_ahub_runtime_suspend()
1329 clk_disable_unprepare(ahub->clk); in tegra_ahub_runtime_suspend()
1331 return 0; in tegra_ahub_runtime_suspend()
1339 err = clk_prepare_enable(ahub->clk); in tegra_ahub_runtime_resume()
1345 regcache_cache_only(ahub->regmap, false); in tegra_ahub_runtime_resume()
1346 regcache_sync(ahub->regmap); in tegra_ahub_runtime_resume()
1348 return 0; in tegra_ahub_runtime_resume()
1357 ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL); in tegra_ahub_probe()
1359 return -ENOMEM; in tegra_ahub_probe()
1361 ahub->soc_data = of_device_get_match_data(&pdev->dev); in tegra_ahub_probe()
1365 ahub->clk = devm_clk_get(&pdev->dev, "ahub"); in tegra_ahub_probe()
1366 if (IS_ERR(ahub->clk)) { in tegra_ahub_probe()
1367 dev_err(&pdev->dev, "can't retrieve AHUB clock\n"); in tegra_ahub_probe()
1368 return PTR_ERR(ahub->clk); in tegra_ahub_probe()
1371 regs = devm_platform_ioremap_resource(pdev, 0); in tegra_ahub_probe()
1375 ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in tegra_ahub_probe()
1376 ahub->soc_data->regmap_config); in tegra_ahub_probe()
1377 if (IS_ERR(ahub->regmap)) { in tegra_ahub_probe()
1378 dev_err(&pdev->dev, "regmap init failed\n"); in tegra_ahub_probe()
1379 return PTR_ERR(ahub->regmap); in tegra_ahub_probe()
1382 regcache_cache_only(ahub->regmap, true); in tegra_ahub_probe()
1384 err = devm_snd_soc_register_component(&pdev->dev, in tegra_ahub_probe()
1385 ahub->soc_data->cmpnt_drv, in tegra_ahub_probe()
1386 ahub->soc_data->dai_drv, in tegra_ahub_probe()
1387 ahub->soc_data->num_dais); in tegra_ahub_probe()
1389 dev_err(&pdev->dev, "can't register AHUB component, err: %d\n", in tegra_ahub_probe()
1394 pm_runtime_enable(&pdev->dev); in tegra_ahub_probe()
1396 err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); in tegra_ahub_probe()
1398 pm_runtime_disable(&pdev->dev); in tegra_ahub_probe()
1402 return 0; in tegra_ahub_probe()
1407 pm_runtime_disable(&pdev->dev); in tegra_ahub_remove()
1421 .name = "tegra210-ahub",