soc/tegra/tegra20_spdif.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6  * Copyright (C) 2011 - NVIDIA, Inc.
9  * Copyright (c) 2008-2009, NVIDIA Corporation
75 /* Interrupt when RX user FIFO attention level is reached */
78 /* Interrupt when TX user FIFO attention level is reached */
81 /* Interrupt when RX data FIFO attention level is reached */
84 /* Interrupt when TX data FIFO attention level is reached */
124  * Receiver(RX) shifter is busy receiving data.
134  * Transmitter(TX) shifter is busy transmitting data.
144  * data from CH_STA_TX_A register is loaded into the internal shifter.
147  * (b) CH_STA_TX_F register is loaded into the internal shifter.
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
184  * 1=attention level reached, 0=attention level not reached.
190  * 1=attention level reached, 0=attention level not reached.
196  * 1=attention level reached, 0=attention level not reached.
202  * 1=attention level reached, 0=attention level not reached.
210  * bi-phase period.
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
219  * Manual data strobe time within the bi-phase clock period (in terms of
220  * the number of over-sampling clocks).
226  * Manual SPDIFIN bi-phase clock period (in terms of the number of
227  * over-sampling clocks).
242 /* RU FIFO attention level */
262 /* TU FIFO attention level */
287 /* RU FIFO attention level */
307 /* TU FIFO attention level */
328  * 16-bit        (BIT_MODE=00, PACK=0)
329  * 20-bit        (BIT_MODE=01, PACK=0)
330  * 24-bit        (BIT_MODE=10, PACK=0)
332  * 16-bit packed (BIT_MODE=00, PACK=1)
368  * 16-bit        (BIT_MODE=00, PACK=0)
369  * 20-bit        (BIT_MODE=01, PACK=0)
370  * 24-bit        (BIT_MODE=10, PACK=0)
372  * 16-bit packed (BIT_MODE=00, PACK=1)
374  * Bits 31:24 are common to all modes except 16-bit packed
417  * The 6-word receive channel data page buffer holds a block (192 frames) of
430  * The 6-word transmit channel data page buffer holds a block (192 frames) of
438  * This 4-word deep FIFO receives user FIFO field information. The order of
445  * This 4-word deep FIFO transmits user FIFO field information. The order of