Lines Matching +full:tegra20 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_spdif.c - Tegra20 SPDIF driver
6 * Copyright (C) 2011-2012 - NVIDIA, Inc.
32 regcache_cache_only(spdif->regmap, true); in tegra20_spdif_runtime_suspend()
34 clk_disable_unprepare(spdif->clk_spdif_out); in tegra20_spdif_runtime_suspend()
44 ret = reset_control_assert(spdif->reset); in tegra20_spdif_runtime_resume()
48 ret = clk_prepare_enable(spdif->clk_spdif_out); in tegra20_spdif_runtime_resume()
56 ret = reset_control_deassert(spdif->reset); in tegra20_spdif_runtime_resume()
60 regcache_cache_only(spdif->regmap, false); in tegra20_spdif_runtime_resume()
61 regcache_mark_dirty(spdif->regmap); in tegra20_spdif_runtime_resume()
63 ret = regcache_sync(spdif->regmap); in tegra20_spdif_runtime_resume()
70 clk_disable_unprepare(spdif->clk_spdif_out); in tegra20_spdif_runtime_resume()
79 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev); in tegra20_spdif_hw_params()
92 return -EINVAL; in tegra20_spdif_hw_params()
95 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val); in tegra20_spdif_hw_params()
101 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR, in tegra20_spdif_hw_params()
128 return -EINVAL; in tegra20_spdif_hw_params()
131 ret = clk_set_rate(spdif->clk_spdif_out, spdifclock); in tegra20_spdif_hw_params()
133 dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret); in tegra20_spdif_hw_params()
137 rate = clk_get_rate(spdif->clk_spdif_out); in tegra20_spdif_hw_params()
139 dev_warn_once(dai->dev, in tegra20_spdif_hw_params()
148 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, in tegra20_spdif_start_playback()
155 regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, in tegra20_spdif_stop_playback()
162 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev); in tegra20_spdif_trigger()
176 return -EINVAL; in tegra20_spdif_trigger()
185 struct snd_interval *r = hw_param_interval(params, rule->var); in tegra20_spdif_filter_rates()
186 struct snd_soc_dai *dai = rule->private; in tegra20_spdif_filter_rates()
187 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev); in tegra20_spdif_filter_rates()
188 struct clk *parent = clk_get_parent(spdif->clk_spdif_out); in tegra20_spdif_filter_rates()
194 dev_err(dai->dev, "Can't get parent clock rate\n"); in tegra20_spdif_filter_rates()
195 return -EINVAL; in tegra20_spdif_filter_rates()
208 valid_rates = BIT(ARRAY_SIZE(rates)) - 1; in tegra20_spdif_filter_rates()
216 if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate")) in tegra20_spdif_startup()
220 * SPDIF and I2S share audio PLL. HDMI takes audio packets from SPDIF in tegra20_spdif_startup()
223 * PLL rate is controlled by I2S side. Filter out audio rates that in tegra20_spdif_startup()
225 * and I2S work simultaneously, assuming that PLL rate won't be in tegra20_spdif_startup()
228 return snd_pcm_hw_rule_add(substream->runtime, 0, in tegra20_spdif_startup()
231 SNDRV_PCM_HW_PARAM_RATE, -1); in tegra20_spdif_startup()
236 struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev); in tegra20_spdif_probe()
238 snd_soc_dai_init_dma_data(dai, &spdif->playback_dma_data, NULL); in tegra20_spdif_probe()
251 .name = "tegra20-spdif",
264 .name = "tegra20-spdif",
350 spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif), in tegra20_spdif_platform_probe()
353 return -ENOMEM; in tegra20_spdif_platform_probe()
355 dev_set_drvdata(&pdev->dev, spdif); in tegra20_spdif_platform_probe()
357 spdif->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); in tegra20_spdif_platform_probe()
358 if (IS_ERR(spdif->reset)) { in tegra20_spdif_platform_probe()
359 dev_err(&pdev->dev, "Can't retrieve spdif reset\n"); in tegra20_spdif_platform_probe()
360 return PTR_ERR(spdif->reset); in tegra20_spdif_platform_probe()
363 spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out"); in tegra20_spdif_platform_probe()
364 if (IS_ERR(spdif->clk_spdif_out)) { in tegra20_spdif_platform_probe()
365 dev_err(&pdev->dev, "Could not retrieve spdif clock\n"); in tegra20_spdif_platform_probe()
366 return PTR_ERR(spdif->clk_spdif_out); in tegra20_spdif_platform_probe()
373 spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in tegra20_spdif_platform_probe()
375 if (IS_ERR(spdif->regmap)) { in tegra20_spdif_platform_probe()
376 dev_err(&pdev->dev, "regmap init failed\n"); in tegra20_spdif_platform_probe()
377 return PTR_ERR(spdif->regmap); in tegra20_spdif_platform_probe()
380 spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT; in tegra20_spdif_platform_probe()
381 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra20_spdif_platform_probe()
382 spdif->playback_dma_data.maxburst = 4; in tegra20_spdif_platform_probe()
384 ret = devm_pm_runtime_enable(&pdev->dev); in tegra20_spdif_platform_probe()
388 ret = devm_snd_soc_register_component(&pdev->dev, in tegra20_spdif_platform_probe()
392 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); in tegra20_spdif_platform_probe()
396 ret = devm_tegra_pcm_platform_register(&pdev->dev); in tegra20_spdif_platform_probe()
398 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); in tegra20_spdif_platform_probe()
413 { .compatible = "nvidia,tegra20-spdif", },
420 .name = "tegra20-spdif",
429 MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");