Lines Matching +full:tegra20 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_i2s.c - Tegra20 I2S driver
6 * Copyright (C) 2010,2012 - NVIDIA, Inc.
10 * Copyright (c) 2009-2010, NVIDIA Corporation.
35 #define DRV_NAME "tegra20-i2s"
39 struct tegra20_i2s *i2s = dev_get_drvdata(dev); in tegra20_i2s_runtime_suspend() local
41 regcache_cache_only(i2s->regmap, true); in tegra20_i2s_runtime_suspend()
43 clk_disable_unprepare(i2s->clk_i2s); in tegra20_i2s_runtime_suspend()
50 struct tegra20_i2s *i2s = dev_get_drvdata(dev); in tegra20_i2s_runtime_resume() local
53 ret = reset_control_assert(i2s->reset); in tegra20_i2s_runtime_resume()
57 ret = clk_prepare_enable(i2s->clk_i2s); in tegra20_i2s_runtime_resume()
65 ret = reset_control_deassert(i2s->reset); in tegra20_i2s_runtime_resume()
69 regcache_cache_only(i2s->regmap, false); in tegra20_i2s_runtime_resume()
70 regcache_mark_dirty(i2s->regmap); in tegra20_i2s_runtime_resume()
72 ret = regcache_sync(i2s->regmap); in tegra20_i2s_runtime_resume()
79 clk_disable_unprepare(i2s->clk_i2s); in tegra20_i2s_runtime_resume()
87 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra20_i2s_set_fmt() local
94 return -EINVAL; in tegra20_i2s_set_fmt()
105 return -EINVAL; in tegra20_i2s_set_fmt()
132 return -EINVAL; in tegra20_i2s_set_fmt()
135 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); in tegra20_i2s_set_fmt()
144 struct device *dev = dai->dev; in tegra20_i2s_hw_params()
145 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra20_i2s_hw_params() local
164 return -EINVAL; in tegra20_i2s_hw_params()
170 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); in tegra20_i2s_hw_params()
177 ret = clk_set_rate(i2s->clk_i2s, i2sclock); in tegra20_i2s_hw_params()
179 dev_err(dev, "Can't set I2S clock rate: %d\n", ret); in tegra20_i2s_hw_params()
183 bitcnt = (i2sclock / (2 * srate)) - 1; in tegra20_i2s_hw_params()
185 return -EINVAL; in tegra20_i2s_hw_params()
191 regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val); in tegra20_i2s_hw_params()
193 regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR, in tegra20_i2s_hw_params()
200 static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s) in tegra20_i2s_start_playback() argument
202 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, in tegra20_i2s_start_playback()
207 static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s) in tegra20_i2s_stop_playback() argument
209 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, in tegra20_i2s_stop_playback()
213 static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s) in tegra20_i2s_start_capture() argument
215 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, in tegra20_i2s_start_capture()
220 static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s) in tegra20_i2s_stop_capture() argument
222 regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, in tegra20_i2s_stop_capture()
229 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra20_i2s_trigger() local
235 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra20_i2s_trigger()
236 tegra20_i2s_start_playback(i2s); in tegra20_i2s_trigger()
238 tegra20_i2s_start_capture(i2s); in tegra20_i2s_trigger()
243 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra20_i2s_trigger()
244 tegra20_i2s_stop_playback(i2s); in tegra20_i2s_trigger()
246 tegra20_i2s_stop_capture(i2s); in tegra20_i2s_trigger()
249 return -EINVAL; in tegra20_i2s_trigger()
257 struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra20_i2s_probe() local
259 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, in tegra20_i2s_probe()
260 &i2s->capture_dma_data); in tegra20_i2s_probe()
272 struct snd_interval *r = hw_param_interval(params, rule->var); in tegra20_i2s_filter_rates()
273 struct snd_soc_dai *dai = rule->private; in tegra20_i2s_filter_rates()
274 struct tegra20_i2s *i2s = dev_get_drvdata(dai->dev); in tegra20_i2s_filter_rates() local
275 struct clk *parent = clk_get_parent(i2s->clk_i2s); in tegra20_i2s_filter_rates()
280 dev_err(dai->dev, "Can't get parent clock rate\n"); in tegra20_i2s_filter_rates()
281 return -EINVAL; in tegra20_i2s_filter_rates()
294 valid_rates = BIT(ARRAY_SIZE(tegra20_i2s_rates)) - 1; in tegra20_i2s_filter_rates()
303 if (!device_property_read_bool(dai->dev, "nvidia,fixed-parent-rate")) in tegra20_i2s_startup()
306 return snd_pcm_hw_rule_add(substream->runtime, 0, in tegra20_i2s_startup()
309 SNDRV_PCM_HW_PARAM_RATE, -1); in tegra20_i2s_startup()
401 struct tegra20_i2s *i2s; in tegra20_i2s_platform_probe() local
406 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL); in tegra20_i2s_platform_probe()
407 if (!i2s) { in tegra20_i2s_platform_probe()
408 ret = -ENOMEM; in tegra20_i2s_platform_probe()
411 dev_set_drvdata(&pdev->dev, i2s); in tegra20_i2s_platform_probe()
413 i2s->dai = tegra20_i2s_dai_template; in tegra20_i2s_platform_probe()
414 i2s->dai.name = dev_name(&pdev->dev); in tegra20_i2s_platform_probe()
416 i2s->reset = devm_reset_control_get_exclusive(&pdev->dev, "i2s"); in tegra20_i2s_platform_probe()
417 if (IS_ERR(i2s->reset)) { in tegra20_i2s_platform_probe()
418 dev_err(&pdev->dev, "Can't retrieve i2s reset\n"); in tegra20_i2s_platform_probe()
419 return PTR_ERR(i2s->reset); in tegra20_i2s_platform_probe()
422 i2s->clk_i2s = devm_clk_get(&pdev->dev, NULL); in tegra20_i2s_platform_probe()
423 if (IS_ERR(i2s->clk_i2s)) { in tegra20_i2s_platform_probe()
424 dev_err(&pdev->dev, "Can't retrieve i2s clock\n"); in tegra20_i2s_platform_probe()
425 ret = PTR_ERR(i2s->clk_i2s); in tegra20_i2s_platform_probe()
435 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in tegra20_i2s_platform_probe()
437 if (IS_ERR(i2s->regmap)) { in tegra20_i2s_platform_probe()
438 dev_err(&pdev->dev, "regmap init failed\n"); in tegra20_i2s_platform_probe()
439 ret = PTR_ERR(i2s->regmap); in tegra20_i2s_platform_probe()
443 i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2; in tegra20_i2s_platform_probe()
444 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra20_i2s_platform_probe()
445 i2s->capture_dma_data.maxburst = 4; in tegra20_i2s_platform_probe()
447 i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1; in tegra20_i2s_platform_probe()
448 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra20_i2s_platform_probe()
449 i2s->playback_dma_data.maxburst = 4; in tegra20_i2s_platform_probe()
451 pm_runtime_enable(&pdev->dev); in tegra20_i2s_platform_probe()
453 ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component, in tegra20_i2s_platform_probe()
454 &i2s->dai, 1); in tegra20_i2s_platform_probe()
456 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); in tegra20_i2s_platform_probe()
457 ret = -ENOMEM; in tegra20_i2s_platform_probe()
461 ret = tegra_pcm_platform_register(&pdev->dev); in tegra20_i2s_platform_probe()
463 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); in tegra20_i2s_platform_probe()
470 snd_soc_unregister_component(&pdev->dev); in tegra20_i2s_platform_probe()
472 pm_runtime_disable(&pdev->dev); in tegra20_i2s_platform_probe()
479 tegra_pcm_platform_unregister(&pdev->dev); in tegra20_i2s_platform_remove()
480 snd_soc_unregister_component(&pdev->dev); in tegra20_i2s_platform_remove()
481 pm_runtime_disable(&pdev->dev); in tegra20_i2s_platform_remove()
485 { .compatible = "nvidia,tegra20-i2s", },
508 MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");