Lines Matching +full:mclk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
78 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0) argument
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
93 /* Defines required for sun8i-h3 support */
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
133 /* Defines required for sun50i-h6 support */
137 #define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
139 #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
157 * struct sun4i_i2s_quirks - Differences between SoC variants.
162 * @field_clkdiv_mclk_en: regmap field to enable mclk output.
169 * @mclk_dividers: mclk dividers array
170 * @num_mclk_dividers: number of mclk dividers
234 u8 div; member
239 { .div = 2, .val = 0 },
240 { .div = 4, .val = 1 },
241 { .div = 6, .val = 2 },
242 { .div = 8, .val = 3 },
243 { .div = 12, .val = 4 },
244 { .div = 16, .val = 5 },
245 /* TODO - extend divide ratio supported by newer SoCs */
249 { .div = 1, .val = 0 },
250 { .div = 2, .val = 1 },
251 { .div = 4, .val = 2 },
252 { .div = 6, .val = 3 },
253 { .div = 8, .val = 4 },
254 { .div = 12, .val = 5 },
255 { .div = 16, .val = 6 },
256 { .div = 24, .val = 7 },
257 /* TODO - extend divide ratio supported by newer SoCs */
261 { .div = 1, .val = 1 },
262 { .div = 2, .val = 2 },
263 { .div = 4, .val = 3 },
264 { .div = 6, .val = 4 },
265 { .div = 8, .val = 5 },
266 { .div = 12, .val = 6 },
267 { .div = 16, .val = 7 },
268 { .div = 24, .val = 8 },
269 { .div = 32, .val = 9 },
270 { .div = 48, .val = 10 },
271 { .div = 64, .val = 11 },
272 { .div = 96, .val = 12 },
273 { .div = 128, .val = 13 },
274 { .div = 176, .val = 14 },
275 { .div = 192, .val = 15 },
280 return i2s->mclk_freq; in sun4i_i2s_get_bclk_parent_rate()
285 return clk_get_rate(i2s->mod_clk); in sun8i_i2s_get_bclk_parent_rate()
294 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; in sun4i_i2s_get_bclk_div()
295 int div = parent_rate / sampling_rate / word_size / channels; in sun4i_i2s_get_bclk_div() local
298 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { in sun4i_i2s_get_bclk_div()
301 if (bdiv->div == div) in sun4i_i2s_get_bclk_div()
302 return bdiv->val; in sun4i_i2s_get_bclk_div()
305 return -EINVAL; in sun4i_i2s_get_bclk_div()
312 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; in sun4i_i2s_get_mclk_div()
313 int div = parent_rate / mclk_rate; in sun4i_i2s_get_mclk_div() local
316 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { in sun4i_i2s_get_mclk_div()
319 if (mdiv->div == div) in sun4i_i2s_get_mclk_div()
320 return mdiv->val; in sun4i_i2s_get_mclk_div()
323 return -EINVAL; in sun4i_i2s_get_mclk_div()
371 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); in sun4i_i2s_set_clk_rate()
372 return -EINVAL; in sun4i_i2s_set_clk_rate()
375 ret = clk_set_rate(i2s->mod_clk, clk_rate); in sun4i_i2s_set_clk_rate()
379 oversample_rate = i2s->mclk_freq / rate; in sun4i_i2s_set_clk_rate()
381 dev_err(dai->dev, "Unsupported oversample rate: %d\n", in sun4i_i2s_set_clk_rate()
383 return -EINVAL; in sun4i_i2s_set_clk_rate()
386 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); in sun4i_i2s_set_clk_rate()
390 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); in sun4i_i2s_set_clk_rate()
391 return -EINVAL; in sun4i_i2s_set_clk_rate()
394 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); in sun4i_i2s_set_clk_rate()
396 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); in sun4i_i2s_set_clk_rate()
397 return -EINVAL; in sun4i_i2s_set_clk_rate()
400 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, in sun4i_i2s_set_clk_rate()
404 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); in sun4i_i2s_set_clk_rate()
420 return -EINVAL; in sun4i_i2s_get_sr()
436 return -EINVAL; in sun4i_i2s_get_wss()
458 return -EINVAL; in sun8i_i2s_get_sr_wss()
466 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun4i_i2s_set_chan_cfg()
467 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); in sun4i_i2s_set_chan_cfg()
470 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
473 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
487 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
488 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
491 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
494 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
498 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
501 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
505 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun8i_i2s_set_chan_cfg()
518 return -EINVAL; in sun8i_i2s_set_chan_cfg()
521 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_chan_cfg()
525 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
539 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98); in sun50i_h6_i2s_set_chan_cfg()
540 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210); in sun50i_h6_i2s_set_chan_cfg()
541 if (i2s->variant->num_din_pins > 1) { in sun50i_h6_i2s_set_chan_cfg()
542 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C); in sun50i_h6_i2s_set_chan_cfg()
543 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908); in sun50i_h6_i2s_set_chan_cfg()
544 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504); in sun50i_h6_i2s_set_chan_cfg()
545 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100); in sun50i_h6_i2s_set_chan_cfg()
547 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); in sun50i_h6_i2s_set_chan_cfg()
548 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); in sun50i_h6_i2s_set_chan_cfg()
552 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), in sun50i_h6_i2s_set_chan_cfg()
555 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, in sun50i_h6_i2s_set_chan_cfg()
559 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun50i_h6_i2s_set_chan_cfg()
562 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun50i_h6_i2s_set_chan_cfg()
566 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun50i_h6_i2s_set_chan_cfg()
579 return -EINVAL; in sun50i_h6_i2s_set_chan_cfg()
582 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun50i_h6_i2s_set_chan_cfg()
586 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), in sun50i_h6_i2s_set_chan_cfg()
607 if (i2s->slots) in sun4i_i2s_hw_params()
608 slots = i2s->slots; in sun4i_i2s_hw_params()
610 if (i2s->slot_width) in sun4i_i2s_hw_params()
611 slot_width = i2s->slot_width; in sun4i_i2s_hw_params()
613 ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width); in sun4i_i2s_hw_params()
615 dev_err(dai->dev, "Invalid channel configuration\n"); in sun4i_i2s_hw_params()
620 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_hw_params()
634 dev_err(dai->dev, "Unsupported physical sample width: %d\n", in sun4i_i2s_hw_params()
636 return -EINVAL; in sun4i_i2s_hw_params()
638 i2s->playback_dma_data.addr_width = width; in sun4i_i2s_hw_params()
640 sr = i2s->variant->get_sr(word_size); in sun4i_i2s_hw_params()
642 return -EINVAL; in sun4i_i2s_hw_params()
644 wss = i2s->variant->get_wss(slot_width); in sun4i_i2s_hw_params()
646 return -EINVAL; in sun4i_i2s_hw_params()
648 regmap_field_write(i2s->field_fmt_wss, wss); in sun4i_i2s_hw_params()
649 regmap_field_write(i2s->field_fmt_sr, sr); in sun4i_i2s_hw_params()
679 return -EINVAL; in sun4i_i2s_set_soc_fmt()
682 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
702 return -EINVAL; in sun4i_i2s_set_soc_fmt()
705 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
721 return -EINVAL; in sun4i_i2s_set_soc_fmt()
723 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_set_soc_fmt()
768 return -EINVAL; in sun8i_i2s_set_soc_fmt()
771 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
773 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
776 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
801 return -EINVAL; in sun8i_i2s_set_soc_fmt()
804 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_soc_fmt()
822 return -EINVAL; in sun8i_i2s_set_soc_fmt()
825 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
830 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, in sun8i_i2s_set_soc_fmt()
876 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
879 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun50i_h6_i2s_set_soc_fmt()
881 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun50i_h6_i2s_set_soc_fmt()
884 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, in sun50i_h6_i2s_set_soc_fmt()
909 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
912 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun50i_h6_i2s_set_soc_fmt()
931 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
934 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun50i_h6_i2s_set_soc_fmt()
939 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, in sun50i_h6_i2s_set_soc_fmt()
951 ret = i2s->variant->set_fmt(i2s, fmt); in sun4i_i2s_set_fmt()
953 dev_err(dai->dev, "Unsupported format configuration\n"); in sun4i_i2s_set_fmt()
957 i2s->format = fmt; in sun4i_i2s_set_fmt()
965 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_capture()
970 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); in sun4i_i2s_start_capture()
973 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_capture()
978 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_capture()
986 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_playback()
991 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); in sun4i_i2s_start_playback()
994 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_playback()
999 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_playback()
1007 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_capture()
1012 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_capture()
1020 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_playback()
1025 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_playback()
1039 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
1048 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
1055 return -EINVAL; in sun4i_i2s_trigger()
1067 return -EINVAL; in sun4i_i2s_set_sysclk()
1069 i2s->mclk_freq = freq; in sun4i_i2s_set_sysclk()
1081 return -EINVAL; in sun4i_i2s_set_tdm_slot()
1083 i2s->slots = slots; in sun4i_i2s_set_tdm_slot()
1084 i2s->slot_width = slot_width; in sun4i_i2s_set_tdm_slot()
1094 &i2s->playback_dma_data, in sun4i_i2s_dai_probe()
1095 &i2s->capture_dma_data); in sun4i_i2s_dai_probe()
1103 struct snd_pcm_runtime *runtime = sub->runtime; in sun4i_i2s_dai_startup()
1106 i2s->variant->pcm_formats); in sun4i_i2s_dai_startup()
1144 .name = "sun4i-dai",
1301 ret = clk_prepare_enable(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1307 regcache_cache_only(i2s->regmap, false); in sun4i_i2s_runtime_resume()
1308 regcache_mark_dirty(i2s->regmap); in sun4i_i2s_runtime_resume()
1310 ret = regcache_sync(i2s->regmap); in sun4i_i2s_runtime_resume()
1317 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1321 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1325 ret = clk_prepare_enable(i2s->mod_clk); in sun4i_i2s_runtime_resume()
1334 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1342 clk_disable_unprepare(i2s->mod_clk); in sun4i_i2s_runtime_suspend()
1345 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1349 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1352 regcache_cache_only(i2s->regmap, true); in sun4i_i2s_runtime_suspend()
1354 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_suspend()
1505 i2s->field_clkdiv_mclk_en = in sun4i_i2s_init_regmap_fields()
1506 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1507 i2s->variant->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1508 if (IS_ERR(i2s->field_clkdiv_mclk_en)) in sun4i_i2s_init_regmap_fields()
1509 return PTR_ERR(i2s->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1511 i2s->field_fmt_wss = in sun4i_i2s_init_regmap_fields()
1512 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1513 i2s->variant->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1514 if (IS_ERR(i2s->field_fmt_wss)) in sun4i_i2s_init_regmap_fields()
1515 return PTR_ERR(i2s->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1517 i2s->field_fmt_sr = in sun4i_i2s_init_regmap_fields()
1518 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1519 i2s->variant->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1520 if (IS_ERR(i2s->field_fmt_sr)) in sun4i_i2s_init_regmap_fields()
1521 return PTR_ERR(i2s->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1533 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); in sun4i_i2s_probe()
1535 return -ENOMEM; in sun4i_i2s_probe()
1546 i2s->variant = of_device_get_match_data(&pdev->dev); in sun4i_i2s_probe()
1547 if (!i2s->variant) { in sun4i_i2s_probe()
1548 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); in sun4i_i2s_probe()
1549 return -ENODEV; in sun4i_i2s_probe()
1552 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); in sun4i_i2s_probe()
1553 if (IS_ERR(i2s->bus_clk)) { in sun4i_i2s_probe()
1554 dev_err(&pdev->dev, "Can't get our bus clock\n"); in sun4i_i2s_probe()
1555 return PTR_ERR(i2s->bus_clk); in sun4i_i2s_probe()
1558 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in sun4i_i2s_probe()
1559 i2s->variant->sun4i_i2s_regmap); in sun4i_i2s_probe()
1560 if (IS_ERR(i2s->regmap)) { in sun4i_i2s_probe()
1561 dev_err(&pdev->dev, "Regmap initialisation failed\n"); in sun4i_i2s_probe()
1562 return PTR_ERR(i2s->regmap); in sun4i_i2s_probe()
1565 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); in sun4i_i2s_probe()
1566 if (IS_ERR(i2s->mod_clk)) { in sun4i_i2s_probe()
1567 dev_err(&pdev->dev, "Can't get our mod clock\n"); in sun4i_i2s_probe()
1568 return PTR_ERR(i2s->mod_clk); in sun4i_i2s_probe()
1571 if (i2s->variant->has_reset) { in sun4i_i2s_probe()
1572 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun4i_i2s_probe()
1573 if (IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1574 dev_err(&pdev->dev, "Failed to get reset control\n"); in sun4i_i2s_probe()
1575 return PTR_ERR(i2s->rst); in sun4i_i2s_probe()
1579 if (!IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1580 ret = reset_control_deassert(i2s->rst); in sun4i_i2s_probe()
1582 dev_err(&pdev->dev, in sun4i_i2s_probe()
1584 return -EINVAL; in sun4i_i2s_probe()
1588 i2s->playback_dma_data.addr = res->start + in sun4i_i2s_probe()
1589 i2s->variant->reg_offset_txdata; in sun4i_i2s_probe()
1590 i2s->playback_dma_data.maxburst = 8; in sun4i_i2s_probe()
1592 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; in sun4i_i2s_probe()
1593 i2s->capture_dma_data.maxburst = 8; in sun4i_i2s_probe()
1595 pm_runtime_enable(&pdev->dev); in sun4i_i2s_probe()
1596 if (!pm_runtime_enabled(&pdev->dev)) { in sun4i_i2s_probe()
1597 ret = sun4i_i2s_runtime_resume(&pdev->dev); in sun4i_i2s_probe()
1602 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); in sun4i_i2s_probe()
1604 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); in sun4i_i2s_probe()
1608 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in sun4i_i2s_probe()
1610 dev_err(&pdev->dev, "Could not register PCM\n"); in sun4i_i2s_probe()
1614 ret = devm_snd_soc_register_component(&pdev->dev, in sun4i_i2s_probe()
1618 dev_err(&pdev->dev, "Could not register DAI\n"); in sun4i_i2s_probe()
1625 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_probe()
1626 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_probe()
1628 pm_runtime_disable(&pdev->dev); in sun4i_i2s_probe()
1629 if (!IS_ERR(i2s->rst)) in sun4i_i2s_probe()
1630 reset_control_assert(i2s->rst); in sun4i_i2s_probe()
1637 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); in sun4i_i2s_remove()
1639 pm_runtime_disable(&pdev->dev); in sun4i_i2s_remove()
1640 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_remove()
1641 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_remove()
1643 if (!IS_ERR(i2s->rst)) in sun4i_i2s_remove()
1644 reset_control_assert(i2s->rst); in sun4i_i2s_remove()
1649 .compatible = "allwinner,sun4i-a10-i2s",
1653 .compatible = "allwinner,sun6i-a31-i2s",
1657 .compatible = "allwinner,sun8i-a83t-i2s",
1661 .compatible = "allwinner,sun8i-h3-i2s",
1665 .compatible = "allwinner,sun50i-a64-codec-i2s",
1669 .compatible = "allwinner,sun50i-h6-i2s",
1673 .compatible = "allwinner,sun50i-r329-i2s",
1689 .name = "sun4i-i2s",
1697 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");