Lines Matching +full:0 +full:xa00000
23 #define ADSP_CFGREG_SW_RSTN 0x0000
24 #define SW_DBG_RSTN_C0 BIT(0)
26 #define ADSP_HIFI_IO_CONFIG 0x000C
29 #define ADSP_IRQ_MASK 0x0030
30 #define ADSP_DVFSRC_REQ 0x0040
31 #define ADSP_DDREN_REQ_0 0x0044
32 #define ADSP_SEMAPHORE 0x0064
33 #define ADSP_WDT_CON_C0 0x007C
34 #define ADSP_MBOX_IRQ_EN 0x009C
35 #define DSP_MBOX0_IRQ_EN BIT(0)
40 #define DSP_PDEBUGPC 0x013C
41 #define DSP_PDEBUGDATA 0x0140
42 #define DSP_PDEBUGINST 0x0144
43 #define DSP_PDEBUGLS0STAT 0x0148
44 #define DSP_PDEBUGSTATUS 0x014C
45 #define DSP_PFAULTINFO 0x0150
46 #define ADSP_CK_EN 0x1000
47 #define CORE_CLK_EN BIT(0)
52 #define ADSP_UART_CTRL 0x1010
53 #define UART_BCLK_CG BIT(0)
57 #define ADSP_PRID 0x0
58 #define ADSP_ALTVEC_C0 0x04
59 #define ADSP_ALTVECSEL 0x0C
60 #define MT8188_ADSP_ALTVECSEL_C0 BIT(0)
64 * On MT8188, BIT(1) is not evaluated and on MT8186 BIT(0) is not evaluated:
71 #define ADSP_SRAM_POOL_CON 0x190
72 #define DSP_SRAM_POOL_PD_MASK 0xF00F /* [0:3] and [12:15] */
73 #define DSP_C0_EMI_MAP_ADDR 0xA00 /* ADSP Core0 To EMI Address Remap */
74 #define DSP_C0_DMAEMI_MAP_ADDR 0xA08 /* DMA0 To EMI Address Remap */
77 #define MBOX_OFFSET 0x500000 /* DRAM */
78 #define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */
79 #define DSP_DRAM_SIZE 0xA00000 /* 16M */
82 #define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x4E100000 /* MT8186 DSP view */
83 #define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8186 DSP view */
85 #define DRAM_REMAP_MASK 0xFFF
87 #define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/
88 #define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/