Lines Matching +full:no +full:- +full:reset +full:- +full:during +full:- +full:suspend
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
21 #include <sound/hda-mlink.h>
24 #include "../sof-audio.h"
28 #include "hda-ipc.h"
49 chip = get_chip_info(sdev->pdata); in hda_get_interfaces()
50 switch (chip->hw_ip_version) { in hda_get_interfaces()
91 return interface_mask[sdev->dspless_mode_selected]; in hda_get_interface_mask()
100 if (sdev->dspless_mode_selected) in hda_is_chain_dma_supported()
115 chip = get_chip_info(sdev->pdata); in hda_is_chain_dma_supported()
116 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) in hda_is_chain_dma_supported()
132 u32 reset; in hda_dsp_core_reset_enter() local
135 /* set reset bits for cores */ in hda_dsp_core_reset_enter()
136 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); in hda_dsp_core_reset_enter()
139 reset, reset); in hda_dsp_core_reset_enter()
144 ((adspcs & reset) == reset), in hda_dsp_core_reset_enter()
148 dev_err(sdev->dev, in hda_dsp_core_reset_enter()
154 /* has core entered reset ? */ in hda_dsp_core_reset_enter()
159 dev_err(sdev->dev, in hda_dsp_core_reset_enter()
160 "error: reset enter failed: core_mask %x adspcs 0x%x\n", in hda_dsp_core_reset_enter()
162 ret = -EIO; in hda_dsp_core_reset_enter()
174 /* clear reset bits for cores */ in hda_dsp_core_reset_leave()
189 dev_err(sdev->dev, in hda_dsp_core_reset_leave()
195 /* has core left reset ? */ in hda_dsp_core_reset_leave()
199 dev_err(sdev->dev, in hda_dsp_core_reset_leave()
200 "error: reset leave failed: core_mask %x adspcs 0x%x\n", in hda_dsp_core_reset_leave()
202 ret = -EIO; in hda_dsp_core_reset_leave()
216 /* set reset state */ in hda_dsp_core_stall_reset()
240 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", in hda_dsp_core_is_enabled()
251 /* leave reset state */ in hda_dsp_core_run()
257 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); in hda_dsp_core_run()
266 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", in hda_dsp_core_run()
268 ret = -EIO; in hda_dsp_core_run()
281 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_core_power_up()
282 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_dsp_core_power_up()
288 core_mask &= chip->host_managed_cores_mask; in hda_dsp_core_power_up()
306 dev_err(sdev->dev, in hda_dsp_core_power_up()
317 dev_err(sdev->dev, in hda_dsp_core_power_up()
320 ret = -EIO; in hda_dsp_core_power_up()
343 dev_err(sdev->dev, in hda_dsp_core_power_down()
352 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_enable_core()
353 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_dsp_enable_core()
357 core_mask &= chip->host_managed_cores_mask; in hda_dsp_enable_core()
366 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", in hda_dsp_enable_core()
378 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_core_reset_power_down()
379 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_dsp_core_reset_power_down()
383 core_mask &= chip->host_managed_cores_mask; in hda_dsp_core_reset_power_down()
389 /* place core in reset prior to power down */ in hda_dsp_core_reset_power_down()
392 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", in hda_dsp_core_reset_power_down()
400 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", in hda_dsp_core_reset_power_down()
407 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", in hda_dsp_core_reset_power_down()
409 ret = -EIO; in hda_dsp_core_reset_power_down()
418 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_ipc_int_enable()
419 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_dsp_ipc_int_enable()
421 if (sdev->dspless_mode_selected) in hda_dsp_ipc_int_enable()
425 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, in hda_dsp_ipc_int_enable()
437 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_ipc_int_disable()
438 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_dsp_ipc_int_disable()
440 if (sdev->dspless_mode_selected) in hda_dsp_ipc_int_disable()
448 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, in hda_dsp_ipc_int_disable()
456 struct snd_sof_pdata *pdata = sdev->pdata; in hda_dsp_wait_d0i3c_done()
460 while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset) & in hda_dsp_wait_d0i3c_done()
462 if (!retry--) in hda_dsp_wait_d0i3c_done()
463 return -ETIMEDOUT; in hda_dsp_wait_d0i3c_done()
474 if (pm_ops && pm_ops->set_pm_gate) in hda_dsp_send_pm_gate_ipc()
475 return pm_ops->set_pm_gate(sdev, flags); in hda_dsp_send_pm_gate_ipc()
482 struct snd_sof_pdata *pdata = sdev->pdata; in hda_dsp_update_d0i3c_register()
489 /* Write to D0I3C after Command-In-Progress bit is cleared */ in hda_dsp_update_d0i3c_register()
492 dev_err(sdev->dev, "CIP timeout before D0I3C update!\n"); in hda_dsp_update_d0i3c_register()
497 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset, in hda_dsp_update_d0i3c_register()
509 dev_err(sdev->dev, "CIP timeout after D0I3C update!\n"); in hda_dsp_update_d0i3c_register()
513 reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset); in hda_dsp_update_d0i3c_register()
516 dev_err(sdev->dev, "failed to update D0I3C!\n"); in hda_dsp_update_d0i3c_register()
517 return -EIO; in hda_dsp_update_d0i3c_register()
536 list_for_each_entry(spcm, &sdev->pcm_list, list) { in hda_dsp_d0i3_streaming_applicable()
538 substream = spcm->stream[dir].substream; in hda_dsp_d0i3_streaming_applicable()
539 if (!substream || !substream->runtime) in hda_dsp_d0i3_streaming_applicable()
542 if (!spcm->stream[dir].d0i3_compatible) in hda_dsp_d0i3_streaming_applicable()
563 * 1. D3 -> D0I0 in hda_dsp_set_D0_state()
564 * 2. D0I0 -> D0I3 in hda_dsp_set_D0_state()
565 * 3. D0I3 -> D0I0 in hda_dsp_set_D0_state()
567 switch (sdev->dsp_power_state.state) { in hda_dsp_set_D0_state()
572 /* Follow regular flow for D3 -> D0 transition */ in hda_dsp_set_D0_state()
575 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", in hda_dsp_set_D0_state()
576 sdev->dsp_power_state.state, target_state->state); in hda_dsp_set_D0_state()
577 return -EINVAL; in hda_dsp_set_D0_state()
581 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { in hda_dsp_set_D0_state()
586 * D0I3 for S0Ix suspend, but it can be kept enabled in hda_dsp_set_D0_state()
590 if (!sdev->fw_trace_is_supported || in hda_dsp_set_D0_state()
592 sdev->system_suspend_target != SOF_SUSPEND_NONE) in hda_dsp_set_D0_state()
614 dev_err(sdev->dev, in hda_dsp_set_D0_state()
637 switch (sdev->dsp_power_state.state) { in hda_dsp_state_log()
639 switch (sdev->dsp_power_state.substate) { in hda_dsp_state_log()
641 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n"); in hda_dsp_state_log()
644 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n"); in hda_dsp_state_log()
647 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n", in hda_dsp_state_log()
648 sdev->dsp_power_state.substate); in hda_dsp_state_log()
653 dev_dbg(sdev->dev, "Current DSP power state: D1\n"); in hda_dsp_state_log()
656 dev_dbg(sdev->dev, "Current DSP power state: D2\n"); in hda_dsp_state_log()
659 dev_dbg(sdev->dev, "Current DSP power state: D3\n"); in hda_dsp_state_log()
662 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n", in hda_dsp_state_log()
663 sdev->dsp_power_state.state); in hda_dsp_state_log()
673 * during system suspend/resume.
680 switch (target_state->state) { in hda_dsp_set_power_state()
685 /* The only allowed transition is: D0I0 -> D3 */ in hda_dsp_set_power_state()
686 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && in hda_dsp_set_power_state()
687 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) in hda_dsp_set_power_state()
690 dev_err(sdev->dev, in hda_dsp_set_power_state()
692 sdev->dsp_power_state.state, target_state->state); in hda_dsp_set_power_state()
693 return -EINVAL; in hda_dsp_set_power_state()
695 dev_err(sdev->dev, "error: target state unsupported %d\n", in hda_dsp_set_power_state()
696 target_state->state); in hda_dsp_set_power_state()
697 return -EINVAL; in hda_dsp_set_power_state()
700 dev_err(sdev->dev, in hda_dsp_set_power_state()
702 target_state->state, target_state->substate); in hda_dsp_set_power_state()
706 sdev->dsp_power_state = *target_state; in hda_dsp_set_power_state()
716 * it could be the case that the DSP is in D0I3 during S0 in hda_dsp_set_power_state_ipc3()
721 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && in hda_dsp_set_power_state_ipc3()
722 sdev->system_suspend_target == SOF_SUSPEND_S0IX) in hda_dsp_set_power_state_ipc3()
729 if (target_state->state == sdev->dsp_power_state.state && in hda_dsp_set_power_state_ipc3()
730 target_state->substate == sdev->dsp_power_state.substate) in hda_dsp_set_power_state_ipc3()
741 if (target_state->state == sdev->dsp_power_state.state && in hda_dsp_set_power_state_ipc4()
742 target_state->substate == sdev->dsp_power_state.substate) in hda_dsp_set_power_state_ipc4()
750 * Audio DSP states may transform as below:-
753 * Runtime +---------------------+ Delayed D0i3 work timeout
754 * suspend | +--------------------+
755 * +------------+ D0I0(active) | |
756 * | | <---------------+ |
757 * | +--------> | New IPC | |
758 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
763 * | | | | suspend | | S0IX | |
764 * | | | | | |suspend | |
767 * +-v---+-----------+--v-------+ | | +------+----v----+
768 * | | | +-----------> |
770 * | | +--------------+ |
772 * +----------------------------+ +----------------+
774 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
775 * ignored the suspend trigger. Otherwise the DSP
781 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_suspend()
782 const struct sof_intel_dsp_desc *chip = hda->desc; in hda_suspend()
795 if (sdev->system_suspend_target > SOF_SUSPEND_S3 || in hda_suspend()
796 (chip->hw_ip_version >= SOF_INTEL_ACE_1_0 && in hda_suspend()
797 sdev->system_suspend_target == SOF_SUSPEND_S3)) in hda_suspend()
802 * as well in order to try to re-load the firmware to do a 'cold' boot. in hda_suspend()
804 if (imr_lost || sdev->fw_state == SOF_FW_CRASHED || in hda_suspend()
805 sdev->fw_state == SOF_FW_BOOT_FAILED) in hda_suspend()
806 hda->skip_imr_boot = true; in hda_suspend()
808 ret = chip->disable_interrupts(sdev); in hda_suspend()
812 /* make sure that no irq handler is pending before shutdown */ in hda_suspend()
813 synchronize_irq(sdev->ipc_irq); in hda_suspend()
820 if (sdev->dspless_mode_selected) in hda_suspend()
823 ret = chip->power_down_dsp(sdev); in hda_suspend()
825 dev_err(sdev->dev, "failed to power down DSP during suspend\n"); in hda_suspend()
829 /* reset ref counts for all cores */ in hda_suspend()
830 for (j = 0; j < chip->cores_num; j++) in hda_suspend()
831 sdev->dsp_core_ref_count[j] = 0; in hda_suspend()
845 /* reset controller */ in hda_suspend()
848 dev_err(sdev->dev, in hda_suspend()
849 "error: failed to reset controller during suspend\n"); in hda_suspend()
853 /* display codec can powered off after link reset */ in hda_suspend()
864 /* display codec must be powered before link reset */ in hda_resume()
873 /* reset and start hda controller */ in hda_resume()
876 dev_err(sdev->dev, in hda_resume()
884 if (sdev->system_suspend_target == SOF_SUSPEND_NONE) in hda_resume()
888 if (!sdev->dspless_mode_selected) { in hda_resume()
894 chip = get_chip_info(sdev->pdata); in hda_resume()
895 if (chip && chip->hw_ip_version >= SOF_INTEL_ACE_2_0) in hda_resume()
907 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_resume()
909 struct pci_dev *pci = to_pci_dev(sdev->dev); in hda_dsp_resume()
917 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { in hda_dsp_resume()
920 dev_err(sdev->dev, in hda_dsp_resume()
926 /* set up CORB/RIRB buffers if was on before suspend */ in hda_dsp_resume()
932 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", in hda_dsp_resume()
938 if (hda->l1_disabled) in hda_dsp_resume()
945 disable_irq_wake(pci->irq); in hda_dsp_resume()
949 /* init hda controller. DSP cores will be powered up during fw boot */ in hda_dsp_resume()
965 /* init hda controller. DSP cores will be powered up during fw boot */ in hda_dsp_runtime_resume()
978 if (hbus->codec_powered) { in hda_dsp_runtime_idle()
979 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", in hda_dsp_runtime_idle()
980 (unsigned int)hbus->codec_powered); in hda_dsp_runtime_idle()
981 return -EBUSY; in hda_dsp_runtime_idle()
990 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_runtime_suspend()
996 if (!sdev->dspless_mode_selected) { in hda_dsp_runtime_suspend()
998 cancel_delayed_work_sync(&hda->d0i3_work); in hda_dsp_runtime_suspend()
1012 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_suspend()
1014 struct pci_dev *pci = to_pci_dev(sdev->dev); in hda_dsp_suspend()
1022 if (!sdev->dspless_mode_selected) { in hda_dsp_suspend()
1024 cancel_delayed_work_sync(&hda->d0i3_work); in hda_dsp_suspend()
1031 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", in hda_dsp_suspend()
1038 if (hda->l1_disabled) in hda_dsp_suspend()
1045 /* no link can be powered in s0ix state */ in hda_dsp_suspend()
1048 dev_err(sdev->dev, in hda_dsp_suspend()
1055 enable_irq_wake(pci->irq); in hda_dsp_suspend()
1063 dev_err(bus->dev, "error: suspending dsp\n"); in hda_dsp_suspend()
1079 list_for_each_entry(s, &bus->stream_list, list) { in hda_dsp_check_for_dma_streams()
1084 active_streams |= BIT(s->index); in hda_dsp_check_for_dma_streams()
1096 * suspend flow, and running of this quirk function. in hda_dsp_s5_quirk()
1098 * to reset before calling this function. in hda_dsp_s5_quirk()
1103 * Take controller out of reset to flush DMA in hda_dsp_s5_quirk()
1112 /* Restore state for shutdown, back to reset */ in hda_dsp_s5_quirk()
1128 sdev->system_suspend_target = SOF_SUSPEND_S3; in hda_dsp_shutdown_dma_flush()
1129 ret = snd_sof_suspend(sdev->dev); in hda_dsp_shutdown_dma_flush()
1132 dev_warn(sdev->dev, in hda_dsp_shutdown_dma_flush()
1137 dev_err(sdev->dev, "shutdown recovery failed (%d)\n", ret2); in hda_dsp_shutdown_dma_flush()
1146 sdev->system_suspend_target = SOF_SUSPEND_S3; in hda_dsp_shutdown()
1147 return snd_sof_suspend(sdev->dev); in hda_dsp_shutdown()
1158 dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__); in hda_dsp_set_hw_params_upon_resume()
1169 struct hdac_bus *bus = &hdev->hbus.core; in hda_dsp_d0i3_work()
1170 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); in hda_dsp_d0i3_work()
1177 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ in hda_dsp_d0i3_work()
1185 dev_err_ratelimited(sdev->dev, in hda_dsp_d0i3_work()
1193 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; in hda_dsp_core_get()
1199 dev_err(sdev->dev, "failed to power up core %d with err: %d\n", in hda_dsp_core_get()
1204 /* No need to send IPC for primary core or if FW boot is not complete */ in hda_dsp_core_get()
1205 if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE) in hda_dsp_core_get()
1208 /* No need to continue the set_core_state ops is not available */ in hda_dsp_core_get()
1209 if (!pm_ops->set_core_state) in hda_dsp_core_get()
1213 ret = pm_ops->set_core_state(sdev, core, true); in hda_dsp_core_get()
1215 dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n", in hda_dsp_core_get()
1226 dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1); in hda_dsp_core_get()
1237 hdev = sdev->pdata->hw_pdata; in hda_common_enable_sdw_irq()
1239 if (!hdev->sdw) in hda_common_enable_sdw_irq()
1256 chip = get_chip_info(sdev->pdata); in hda_sdw_int_enable()
1257 if (chip && chip->enable_sdw_irq) in hda_sdw_int_enable()
1258 chip->enable_sdw_irq(sdev, enable); in hda_sdw_int_enable()
1268 hdev = sdev->pdata->hw_pdata; in hda_sdw_check_lcount_common()
1269 ctx = hdev->sdw; in hda_sdw_check_lcount_common()
1271 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); in hda_sdw_check_lcount_common()
1275 if (caps < ctx->count) { in hda_sdw_check_lcount_common()
1276 dev_err(sdev->dev, in hda_sdw_check_lcount_common()
1278 __func__, ctx->count, caps); in hda_sdw_check_lcount_common()
1279 return -EINVAL; in hda_sdw_check_lcount_common()
1295 hdev = sdev->pdata->hw_pdata; in hda_sdw_check_lcount_ext()
1296 ctx = hdev->sdw; in hda_sdw_check_lcount_ext()
1301 if (slcount < ctx->count) { in hda_sdw_check_lcount_ext()
1302 dev_err(sdev->dev, in hda_sdw_check_lcount_ext()
1304 __func__, ctx->count, slcount); in hda_sdw_check_lcount_ext()
1305 return -EINVAL; in hda_sdw_check_lcount_ext()
1316 chip = get_chip_info(sdev->pdata); in hda_sdw_check_lcount()
1317 if (chip && chip->read_sdw_lcount) in hda_sdw_check_lcount()
1318 return chip->read_sdw_lcount(sdev); in hda_sdw_check_lcount()
1332 chip = get_chip_info(sdev->pdata); in hda_sdw_process_wakeen()
1333 if (chip && chip->sdw_process_wakeen) in hda_sdw_process_wakeen()
1334 chip->sdw_process_wakeen(sdev); in hda_sdw_process_wakeen()
1364 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
1490 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); in hda_dsp_get_state()
1494 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); in hda_dsp_get_state()
1508 if (chip->hw_ip_version < SOF_INTEL_ACE_1_0) in hda_dsp_get_state()
1520 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); in hda_dsp_get_state()
1532 dev_printk(level, sdev->dev, in hda_dsp_get_state()
1537 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", in hda_dsp_get_state()
1542 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); in hda_dsp_get_state()
1552 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, in hda_dsp_get_state()
1555 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, in hda_dsp_get_state()
1565 u32 offset = sdev->dsp_oops_offset; in hda_dsp_get_registers()
1573 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { in hda_dsp_get_registers()
1574 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", in hda_dsp_get_registers()
1575 xoops->arch_hdr.totalsize); in hda_dsp_get_registers()
1578 offset += xoops->arch_hdr.totalsize; in hda_dsp_get_registers()
1579 sof_block_read(sdev, sdev->mmio_bar, offset, in hda_dsp_get_registers()
1584 sof_block_read(sdev, sdev->mmio_bar, offset, stack, in hda_dsp_get_registers()
1598 chip = get_chip_info(sdev->pdata); in hda_dsp_dump_ext_rom_status()
1600 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); in hda_dsp_dump_ext_rom_status()
1601 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); in hda_dsp_dump_ext_rom_status()
1604 dev_printk(level, sdev->dev, "extended rom status: %s", msg); in hda_dsp_dump_ext_rom_status()
1619 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { in hda_dsp_dump()