30 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)  in hda_dsp_ctrl_link_reset()  argument
40 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,  in hda_dsp_ctrl_link_reset()
46 		gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);  in hda_dsp_ctrl_link_reset()
53 	dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",  in hda_dsp_ctrl_link_reset()
58 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)  in hda_dsp_ctrl_get_caps()  argument
60 	struct hdac_bus *bus = sof_to_bus(sdev);  in hda_dsp_ctrl_get_caps()
69 	ret = hda_dsp_ctrl_link_reset(sdev, true);  in hda_dsp_ctrl_get_caps()
72 	ret = hda_dsp_ctrl_link_reset(sdev, false);  in hda_dsp_ctrl_get_caps()
76 	offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);  in hda_dsp_ctrl_get_caps()
79 		dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",  in hda_dsp_ctrl_get_caps()
82 		cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);  in hda_dsp_ctrl_get_caps()
93 			dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
96 			sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;  in hda_dsp_ctrl_get_caps()
99 			dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
102 			sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;  in hda_dsp_ctrl_get_caps()
105 			dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
108 			sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;  in hda_dsp_ctrl_get_caps()
111 			dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
116 			dev_dbg(sdev->dev, "found ML capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
121 			dev_dbg(sdev->dev, "found capability %d at 0x%x\n",  in hda_dsp_ctrl_get_caps()
133 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_ppcap_enable()  argument
137 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,  in hda_dsp_ctrl_ppcap_enable()
142 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_ppcap_int_enable()  argument
146 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,  in hda_dsp_ctrl_ppcap_int_enable()
151 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_misc_clock_gating()  argument
155 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);  in hda_dsp_ctrl_misc_clock_gating()
163 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)  in hda_dsp_ctrl_clock_power_gating()  argument
165 	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;  in hda_dsp_ctrl_clock_power_gating()
170 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);  in hda_dsp_ctrl_clock_power_gating()
175 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,  in hda_dsp_ctrl_clock_power_gating()
180 	snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);  in hda_dsp_ctrl_clock_power_gating()
186 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev)  in hda_dsp_ctrl_init_chip()  argument
188 	struct hdac_bus *bus = sof_to_bus(sdev);  in hda_dsp_ctrl_init_chip()
196 	hda_codec_set_codec_wakeup(sdev, true);  in hda_dsp_ctrl_init_chip()
198 	hda_dsp_ctrl_misc_clock_gating(sdev, false);  in hda_dsp_ctrl_init_chip()
201 	gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);  in hda_dsp_ctrl_init_chip()
203 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_init_chip()
207 	ret = hda_dsp_ctrl_link_reset(sdev, true);  in hda_dsp_ctrl_init_chip()
209 		dev_err(sdev->dev, "error: failed to reset HDA controller\n");  in hda_dsp_ctrl_init_chip()
216 	ret = hda_dsp_ctrl_link_reset(sdev, false);  in hda_dsp_ctrl_init_chip()
218 		dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");  in hda_dsp_ctrl_init_chip()
223 	hda_codec_detect_mask(sdev);  in hda_dsp_ctrl_init_chip()
228 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_init_chip()
234 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,  in hda_dsp_ctrl_init_chip()
237 	hda_codec_rirb_status_clear(sdev);  in hda_dsp_ctrl_init_chip()
240 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,  in hda_dsp_ctrl_init_chip()
243 	hda_codec_init_cmd_io(sdev);  in hda_dsp_ctrl_init_chip()
246 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,  in hda_dsp_ctrl_init_chip()
252 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,  in hda_dsp_ctrl_init_chip()
254 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,  in hda_dsp_ctrl_init_chip()
263 	hda_dsp_ctrl_misc_clock_gating(sdev, true);  in hda_dsp_ctrl_init_chip()
265 	hda_codec_set_codec_wakeup(sdev, false);  in hda_dsp_ctrl_init_chip()
271 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)  in hda_dsp_ctrl_stop_chip()  argument
273 	struct hdac_bus *bus = sof_to_bus(sdev);  in hda_dsp_ctrl_stop_chip()
283 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()
291 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,  in hda_dsp_ctrl_stop_chip()
295 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,  in hda_dsp_ctrl_stop_chip()
302 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()
308 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,  in hda_dsp_ctrl_stop_chip()
311 	hda_codec_rirb_status_clear(sdev);  in hda_dsp_ctrl_stop_chip()
314 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,  in hda_dsp_ctrl_stop_chip()
317 	hda_codec_stop_cmd_io(sdev);  in hda_dsp_ctrl_stop_chip()
321 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()
323 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,  in hda_dsp_ctrl_stop_chip()