sof/intel/byt.c

29 	{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
31 	{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
33 	{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
35 	{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
37 	{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
39 	{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
41 	{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
43 	{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
48 	{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
50 	{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
52 	{"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
54 	{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
56 	{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
58 	{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
60 	{"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
62 	{"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
64 	{"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
66 	{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
68 	{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
70 	{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
77 	snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);  in byt_reset_dsp_disable_int()
78 	snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);  in byt_reset_dsp_disable_int()
81 	snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,  in byt_reset_dsp_disable_int()
96 	snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,  in byt_resume()
147 	sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);  in byt_acpi_probe()
148 	if (!sdev->bar[DSP_BAR]) {  in byt_acpi_probe()
153 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);  in byt_acpi_probe()
156 	sdev->mmio_bar = DSP_BAR;  in byt_acpi_probe()
157 	sdev->mailbox_bar = DSP_BAR;  in byt_acpi_probe()
206 	snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,  in byt_acpi_probe()