44 	{ .compatible = "rockchip,rk3066-spdif",
46 	{ .compatible = "rockchip,rk3188-spdif",
48 	{ .compatible = "rockchip,rk3228-spdif",
50 	{ .compatible = "rockchip,rk3288-spdif",
52 	{ .compatible = "rockchip,rk3328-spdif",
54 	{ .compatible = "rockchip,rk3366-spdif",
56 	{ .compatible = "rockchip,rk3368-spdif",
58 	{ .compatible = "rockchip,rk3399-spdif",
60 	{ .compatible = "rockchip,rk3568-spdif",
68 	struct rk_spdif_dev *spdif = dev_get_drvdata(dev);  in rk_spdif_runtime_suspend()  local
70 	regcache_cache_only(spdif->regmap, true);  in rk_spdif_runtime_suspend()
71 	clk_disable_unprepare(spdif->mclk);  in rk_spdif_runtime_suspend()
72 	clk_disable_unprepare(spdif->hclk);  in rk_spdif_runtime_suspend()
79 	struct rk_spdif_dev *spdif = dev_get_drvdata(dev);  in rk_spdif_runtime_resume()  local
82 	ret = clk_prepare_enable(spdif->mclk);  in rk_spdif_runtime_resume()
84 		dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);  in rk_spdif_runtime_resume()
88 	ret = clk_prepare_enable(spdif->hclk);  in rk_spdif_runtime_resume()
90 		clk_disable_unprepare(spdif->mclk);  in rk_spdif_runtime_resume()
91 		dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);  in rk_spdif_runtime_resume()
95 	regcache_cache_only(spdif->regmap, false);  in rk_spdif_runtime_resume()
96 	regcache_mark_dirty(spdif->regmap);  in rk_spdif_runtime_resume()
98 	ret = regcache_sync(spdif->regmap);  in rk_spdif_runtime_resume()
100 		clk_disable_unprepare(spdif->mclk);  in rk_spdif_runtime_resume()
101 		clk_disable_unprepare(spdif->hclk);  in rk_spdif_runtime_resume()
111 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);  in rk_spdif_hw_params()  local
134 	ret = clk_set_rate(spdif->mclk, mclk);  in rk_spdif_hw_params()
136 		dev_err(spdif->dev, "Failed to set module clock rate: %d\n",  in rk_spdif_hw_params()
141 	ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,  in rk_spdif_hw_params()
152 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);  in rk_spdif_trigger()  local
159 		ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,  in rk_spdif_trigger()
168 		ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,  in rk_spdif_trigger()
175 		ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,  in rk_spdif_trigger()
182 		ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,  in rk_spdif_trigger()
196 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);  in rk_spdif_dai_probe()  local
198 	snd_soc_dai_dma_data_set_playback(dai, &spdif->playback_dma_data);  in rk_spdif_dai_probe()
227 	.name = "rockchip-spdif",
286 	struct rk_spdif_dev *spdif;  in rk_spdif_probe()  local
303 		/* Select the 8 channel SPDIF solution on RK3288 as  in rk_spdif_probe()
309 	spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);  in rk_spdif_probe()
310 	if (!spdif)  in rk_spdif_probe()
313 	spdif->hclk = devm_clk_get(&pdev->dev, "hclk");  in rk_spdif_probe()
314 	if (IS_ERR(spdif->hclk))  in rk_spdif_probe()
315 		return PTR_ERR(spdif->hclk);  in rk_spdif_probe()
317 	spdif->mclk = devm_clk_get(&pdev->dev, "mclk");  in rk_spdif_probe()
318 	if (IS_ERR(spdif->mclk))  in rk_spdif_probe()
319 		return PTR_ERR(spdif->mclk);  in rk_spdif_probe()
325 	spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,  in rk_spdif_probe()
327 	if (IS_ERR(spdif->regmap))  in rk_spdif_probe()
328 		return PTR_ERR(spdif->regmap);  in rk_spdif_probe()
330 	spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;  in rk_spdif_probe()
331 	spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in rk_spdif_probe()
332 	spdif->playback_dma_data.maxburst = 4;  in rk_spdif_probe()
334 	spdif->dev = &pdev->dev;  in rk_spdif_probe()
335 	dev_set_drvdata(&pdev->dev, spdif);  in rk_spdif_probe()
385 		.name = "rockchip-spdif",
392 MODULE_ALIAS("platform:rockchip-spdif");
393 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");