1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 #include <sound/soc-dai.h>
80 	regmap_read(priv->map, SPDIFIN_STAT0, &stat);  in axg_spdifin_get_rate()
90 		rate = priv->conf->mode_rates[mode];  in axg_spdifin_get_rate()
101 	regmap_update_bits(priv->map, SPDIFIN_CTRL0,  in axg_spdifin_prepare()
107 	regmap_update_bits(priv->map, SPDIFIN_CTRL0,  in axg_spdifin_prepare()
109 	regmap_update_bits(priv->map, SPDIFIN_CTRL0,  in axg_spdifin_prepare()
127 	shift = width * (num_per_reg - 1 - rem);  in axg_spdifin_write_mode_param()
129 	regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,  in axg_spdifin_write_mode_param()
155 	return rate / (128 * priv->conf->mode_rates[mode]);  in axg_spdifin_mode_timer()
162 	int ret, i = SPDIFIN_MODE_NUM - 1;  in axg_spdifin_sample_mode_config()
165 	ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);  in axg_spdifin_sample_mode_config()
167 		dev_err(dai->dev, "reference clock rate set failed\n");  in axg_spdifin_sample_mode_config()
175 	rate = clk_get_rate(priv->refclk);  in axg_spdifin_sample_mode_config()
178 	regmap_update_bits(priv->map, SPDIFIN_CTRL1,  in axg_spdifin_sample_mode_config()
183 	regmap_update_bits(priv->map, SPDIFIN_CTRL0,  in axg_spdifin_sample_mode_config()
188 	axg_spdifin_write_timer(priv->map, i, t_next);  in axg_spdifin_sample_mode_config()
193 		i -= 1;  in axg_spdifin_sample_mode_config()
199 		axg_spdifin_write_timer(priv->map, i, t);  in axg_spdifin_sample_mode_config()
202 		axg_spdifin_write_threshold(priv->map, i, 3 * (t + t_next));  in axg_spdifin_sample_mode_config()
217 	ret = clk_prepare_enable(priv->pclk);  in axg_spdifin_dai_probe()
219 		dev_err(dai->dev, "failed to enable pclk\n");  in axg_spdifin_dai_probe()
225 		dev_err(dai->dev, "mode configuration failed\n");  in axg_spdifin_dai_probe()
229 	ret = clk_prepare_enable(priv->refclk);  in axg_spdifin_dai_probe()
231 		dev_err(dai->dev,  in axg_spdifin_dai_probe()
232 			"failed to enable spdifin reference clock\n");  in axg_spdifin_dai_probe()
236 	regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,  in axg_spdifin_dai_probe()
242 	clk_disable_unprepare(priv->pclk);  in axg_spdifin_dai_probe()
250 	regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);  in axg_spdifin_dai_remove()
251 	clk_disable_unprepare(priv->refclk);  in axg_spdifin_dai_remove()
252 	clk_disable_unprepare(priv->pclk);  in axg_spdifin_dai_remove()
265 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;  in axg_spdifin_iec958_info()
266 	uinfo->count = 1;  in axg_spdifin_iec958_info()
277 		ucontrol->value.iec958.status[i] = 0xff;  in axg_spdifin_get_status_mask()
292 		regmap_update_bits(priv->map, SPDIFIN_CTRL0,  in axg_spdifin_get_status()
296 		regmap_read(priv->map, SPDIFIN_STAT1, &val);  in axg_spdifin_get_status()
301 			ucontrol->value.iec958.status[offset] =  in axg_spdifin_get_status()
339 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;  in axg_spdifin_rate_lock_info()
340 	uinfo->count = 1;  in axg_spdifin_rate_lock_info()
341 	uinfo->value.integer.min = 0;  in axg_spdifin_rate_lock_info()
342 	uinfo->value.integer.max = 192000;  in axg_spdifin_rate_lock_info()
353 	ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);  in axg_spdifin_rate_lock_get()
401 		.compatible = "amlogic,axg-spdifin",
415 		return ERR_PTR(-ENOMEM);  in axg_spdifin_get_dai_drv()
417 	drv->name = "SPDIF Input";  in axg_spdifin_get_dai_drv()
418 	drv->ops = &axg_spdifin_ops;  in axg_spdifin_get_dai_drv()
419 	drv->capture.stream_name = "Capture";  in axg_spdifin_get_dai_drv()
420 	drv->capture.channels_min = 1;  in axg_spdifin_get_dai_drv()
421 	drv->capture.channels_max = 2;  in axg_spdifin_get_dai_drv()
422 	drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;  in axg_spdifin_get_dai_drv()
426 			snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);  in axg_spdifin_get_dai_drv()
429 			return ERR_PTR(-EINVAL);  in axg_spdifin_get_dai_drv()
431 		drv->capture.rates |= rb;  in axg_spdifin_get_dai_drv()
439 	struct device *dev = &pdev->dev;  in axg_spdifin_probe()
446 		return -ENOMEM;  in axg_spdifin_probe()
449 	priv->conf = of_device_get_match_data(dev);  in axg_spdifin_probe()
450 	if (!priv->conf) {  in axg_spdifin_probe()
452 		return -ENODEV;  in axg_spdifin_probe()
459 	priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);  in axg_spdifin_probe()
460 	if (IS_ERR(priv->map)) {  in axg_spdifin_probe()
462 			PTR_ERR(priv->map));  in axg_spdifin_probe()
463 		return PTR_ERR(priv->map);  in axg_spdifin_probe()
466 	priv->pclk = devm_clk_get(dev, "pclk");  in axg_spdifin_probe()
467 	if (IS_ERR(priv->pclk))  in axg_spdifin_probe()
468 		return dev_err_probe(dev, PTR_ERR(priv->pclk), "failed to get pclk\n");  in axg_spdifin_probe()
470 	priv->refclk = devm_clk_get(dev, "refclk");  in axg_spdifin_probe()
471 	if (IS_ERR(priv->refclk))  in axg_spdifin_probe()
472 		return dev_err_probe(dev, PTR_ERR(priv->refclk), "failed to get mclk\n");  in axg_spdifin_probe()
488 		.name = "axg-spdifin",
494 MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");