3  * MediaTek 8365 AFE clock control
10 #include "mt8365-afe-clk.h"
11 #include "mt8365-afe-common.h"
13 #include "../common/mtk-base-afe.h"
34 int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe)  in mt8365_afe_init_audio_clk()  argument
37 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_init_audio_clk()
40 		afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8365_afe_init_audio_clk()
42 			dev_err(afe->dev, "%s devm_clk_get %s fail\n",  in mt8365_afe_init_audio_clk()
50 void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)  in mt8365_afe_disable_clk()  argument
56 int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,  in mt8365_afe_set_clk_rate()  argument
64 			dev_err(afe->dev, "Failed to set rate\n");  in mt8365_afe_set_clk_rate()
71 int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,  in mt8365_afe_set_clk_parent()  argument
79 			dev_err(afe->dev, "Failed to set parent\n");  in mt8365_afe_set_clk_parent()
192 int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)  in mt8365_afe_enable_top_cg()  argument
194 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_enable_top_cg()
204 		regmap_update_bits(afe->regmap, reg, mask, val);  in mt8365_afe_enable_top_cg()
211 int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)  in mt8365_afe_disable_top_cg()  argument
213 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_disable_top_cg()
223 		regmap_update_bits(afe->regmap, reg, mask, val);  in mt8365_afe_disable_top_cg()
232 int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe)  in mt8365_afe_enable_main_clk()  argument
234 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_enable_main_clk()
237 	mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);  in mt8365_afe_enable_main_clk()
238 	mt8365_afe_enable_afe_on(afe);  in mt8365_afe_enable_main_clk()
243 int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe)  in mt8365_afe_disable_main_clk()  argument
245 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_disable_main_clk()
247 	mt8365_afe_disable_afe_on(afe);  in mt8365_afe_disable_main_clk()
248 	mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);  in mt8365_afe_disable_main_clk()
249 	mt8365_afe_disable_clk(afe, afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);  in mt8365_afe_disable_main_clk()
254 int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe)  in mt8365_afe_emi_clk_on()  argument
259 int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe)  in mt8365_afe_emi_clk_off()  argument
264 int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe)  in mt8365_afe_enable_afe_on()  argument
266 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_enable_afe_on()
273 		regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);  in mt8365_afe_enable_afe_on()
280 int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)  in mt8365_afe_disable_afe_on()  argument
282 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_disable_afe_on()
289 		regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);  in mt8365_afe_disable_afe_on()
298 static int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)  in mt8365_afe_hd_engen_enable()  argument
301 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8365_afe_hd_engen_enable()
304 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8365_afe_hd_engen_enable()
310 static int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)  in mt8365_afe_hd_engen_disable()  argument
313 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8365_afe_hd_engen_disable()
316 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8365_afe_hd_engen_disable()
322 int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)  in mt8365_afe_enable_apll_tuner_cfg()  argument
324 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_enable_apll_tuner_cfg()
335 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,  in mt8365_afe_enable_apll_tuner_cfg()
337 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,  in mt8365_afe_enable_apll_tuner_cfg()
340 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,  in mt8365_afe_enable_apll_tuner_cfg()
342 		regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,  in mt8365_afe_enable_apll_tuner_cfg()
350 int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)  in mt8365_afe_disable_apll_tuner_cfg()  argument
352 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_disable_apll_tuner_cfg()
359 			regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,  in mt8365_afe_disable_apll_tuner_cfg()
362 			regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,  in mt8365_afe_disable_apll_tuner_cfg()
373 int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)  in mt8365_afe_enable_apll_associated_cfg()  argument
375 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_enable_apll_associated_cfg()
379 			dev_info(afe->dev, "%s Failed to enable ENGEN1 clk\n",  in mt8365_afe_enable_apll_associated_cfg()
383 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_22M);  in mt8365_afe_enable_apll_associated_cfg()
384 		mt8365_afe_hd_engen_enable(afe, true);  in mt8365_afe_enable_apll_associated_cfg()
385 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);  in mt8365_afe_enable_apll_associated_cfg()
386 		mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);  in mt8365_afe_enable_apll_associated_cfg()
389 			dev_info(afe->dev, "%s Failed to enable ENGEN2 clk\n",  in mt8365_afe_enable_apll_associated_cfg()
393 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_24M);  in mt8365_afe_enable_apll_associated_cfg()
394 		mt8365_afe_hd_engen_enable(afe, false);  in mt8365_afe_enable_apll_associated_cfg()
395 		mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);  in mt8365_afe_enable_apll_associated_cfg()
396 		mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);  in mt8365_afe_enable_apll_associated_cfg()
402 int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)  in mt8365_afe_disable_apll_associated_cfg()  argument
404 	struct mt8365_afe_private *afe_priv = afe->platform_priv;  in mt8365_afe_disable_apll_associated_cfg()
407 		mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);  in mt8365_afe_disable_apll_associated_cfg()
408 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);  in mt8365_afe_disable_apll_associated_cfg()
409 		mt8365_afe_hd_engen_disable(afe, true);  in mt8365_afe_disable_apll_associated_cfg()
410 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_22M);  in mt8365_afe_disable_apll_associated_cfg()
413 		mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);  in mt8365_afe_disable_apll_associated_cfg()
414 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);  in mt8365_afe_disable_apll_associated_cfg()
415 		mt8365_afe_hd_engen_disable(afe, false);  in mt8365_afe_disable_apll_associated_cfg()
416 		mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_24M);  in mt8365_afe_disable_apll_associated_cfg()