Lines Matching +full:mt8195 +full:- +full:audio
1 // SPDX-License-Identifier: GPL-2.0
3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
12 #include "mt8195-afe-common.h"
13 #include "mt8195-afe-clk.h"
14 #include "mt8195-reg.h"
15 #include "mt8195-audsys-clk.h"
209 return -EINVAL; in mt8195_afe_init_apll_tuner()
211 cfg->ref_cnt = 0; in mt8195_afe_init_apll_tuner()
212 spin_lock_init(&cfg->ctrl_lock); in mt8195_afe_init_apll_tuner()
223 return -EINVAL; in mt8195_afe_setup_apll_tuner()
225 regmap_update_bits(afe->regmap, cfg->apll_div_reg, in mt8195_afe_setup_apll_tuner()
226 cfg->apll_div_maskbit << cfg->apll_div_shift, in mt8195_afe_setup_apll_tuner()
227 cfg->apll_div_default << cfg->apll_div_shift); in mt8195_afe_setup_apll_tuner()
229 regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg, in mt8195_afe_setup_apll_tuner()
230 cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift, in mt8195_afe_setup_apll_tuner()
231 cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift); in mt8195_afe_setup_apll_tuner()
233 regmap_update_bits(afe->regmap, cfg->upper_bound_reg, in mt8195_afe_setup_apll_tuner()
234 cfg->upper_bound_maskbit << cfg->upper_bound_shift, in mt8195_afe_setup_apll_tuner()
235 cfg->upper_bound_default << cfg->upper_bound_shift); in mt8195_afe_setup_apll_tuner()
243 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_enable_tuner_clk()
247 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); in mt8195_afe_enable_tuner_clk()
248 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); in mt8195_afe_enable_tuner_clk()
251 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); in mt8195_afe_enable_tuner_clk()
252 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); in mt8195_afe_enable_tuner_clk()
264 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_disable_tuner_clk()
268 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); in mt8195_afe_disable_tuner_clk()
269 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); in mt8195_afe_disable_tuner_clk()
272 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); in mt8195_afe_disable_tuner_clk()
273 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); in mt8195_afe_disable_tuner_clk()
290 return -EINVAL; in mt8195_afe_enable_apll_tuner()
300 spin_lock_irqsave(&cfg->ctrl_lock, flags); in mt8195_afe_enable_apll_tuner()
302 cfg->ref_cnt++; in mt8195_afe_enable_apll_tuner()
303 if (cfg->ref_cnt == 1) in mt8195_afe_enable_apll_tuner()
304 regmap_update_bits(afe->regmap, in mt8195_afe_enable_apll_tuner()
305 cfg->tuner_en_reg, in mt8195_afe_enable_apll_tuner()
306 cfg->tuner_en_maskbit << cfg->tuner_en_shift, in mt8195_afe_enable_apll_tuner()
307 1 << cfg->tuner_en_shift); in mt8195_afe_enable_apll_tuner()
309 spin_unlock_irqrestore(&cfg->ctrl_lock, flags); in mt8195_afe_enable_apll_tuner()
322 return -EINVAL; in mt8195_afe_disable_apll_tuner()
324 spin_lock_irqsave(&cfg->ctrl_lock, flags); in mt8195_afe_disable_apll_tuner()
326 cfg->ref_cnt--; in mt8195_afe_disable_apll_tuner()
327 if (cfg->ref_cnt == 0) in mt8195_afe_disable_apll_tuner()
328 regmap_update_bits(afe->regmap, in mt8195_afe_disable_apll_tuner()
329 cfg->tuner_en_reg, in mt8195_afe_disable_apll_tuner()
330 cfg->tuner_en_maskbit << cfg->tuner_en_shift, in mt8195_afe_disable_apll_tuner()
331 0 << cfg->tuner_en_shift); in mt8195_afe_disable_apll_tuner()
332 else if (cfg->ref_cnt < 0) in mt8195_afe_disable_apll_tuner()
333 cfg->ref_cnt = 0; in mt8195_afe_disable_apll_tuner()
335 spin_unlock_irqrestore(&cfg->ctrl_lock, flags); in mt8195_afe_disable_apll_tuner()
354 return -EINVAL; in mt8195_afe_get_mclk_source_clk_id()
360 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_get_mclk_source_rate()
364 dev_dbg(afe->dev, "invalid clk id\n"); in mt8195_afe_get_mclk_source_rate()
368 return clk_get_rate(afe_priv->clk[clk_id]); in mt8195_afe_get_mclk_source_rate()
379 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_init_clock()
384 afe_priv->clk = in mt8195_afe_init_clock()
385 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk), in mt8195_afe_init_clock()
387 if (!afe_priv->clk) in mt8195_afe_init_clock()
388 return -ENOMEM; in mt8195_afe_init_clock()
391 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8195_afe_init_clock()
392 if (IS_ERR(afe_priv->clk[i])) { in mt8195_afe_init_clock()
393 dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", in mt8195_afe_init_clock()
395 PTR_ERR(afe_priv->clk[i])); in mt8195_afe_init_clock()
396 return PTR_ERR(afe_priv->clk[i]); in mt8195_afe_init_clock()
404 dev_dbg(afe->dev, "%s(), init apll_tuner%d failed", in mt8195_afe_init_clock()
406 return -EINVAL; in mt8195_afe_init_clock()
420 dev_dbg(afe->dev, "%s(), failed to enable clk\n", in mt8195_afe_enable_clk()
425 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_enable_clk()
436 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_disable_clk()
447 dev_dbg(afe->dev, "%s(), failed to prepare clk\n", in mt8195_afe_prepare_clk()
452 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_prepare_clk()
462 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_unprepare_clk()
472 dev_dbg(afe->dev, "%s(), failed to clk enable\n", in mt8195_afe_enable_clk_atomic()
477 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_enable_clk_atomic()
487 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_disable_clk_atomic()
498 dev_dbg(afe->dev, "%s(), failed to set clk rate\n", in mt8195_afe_set_clk_rate()
515 dev_dbg(afe->dev, "%s(), failed to set clk parent\n", in mt8195_afe_set_clk_parent()
580 regmap_update_bits(afe->regmap, reg, mask, val); in mt8195_afe_enable_top_cg()
590 regmap_update_bits(afe->regmap, reg, mask, val); in mt8195_afe_disable_top_cg()
596 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_enable_reg_rw_clk()
603 MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */ in mt8195_afe_enable_reg_rw_clk()
610 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_enable_reg_rw_clk()
617 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_disable_reg_rw_clk()
631 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_disable_reg_rw_clk()
638 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); in mt8195_afe_enable_afe_on()
644 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); in mt8195_afe_disable_afe_on()
650 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_enable_timing_sys()
663 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_enable_timing_sys()
673 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_disable_timing_sys()
689 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_disable_timing_sys()