Lines Matching full:afe
3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
12 #include "mt8195-afe-common.h"
13 #include "mt8195-afe-clk.h"
41 /* afe clock gate */
217 static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe, in mt8195_afe_setup_apll_tuner() argument
225 regmap_update_bits(afe->regmap, cfg->apll_div_reg, in mt8195_afe_setup_apll_tuner()
229 regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg, in mt8195_afe_setup_apll_tuner()
233 regmap_update_bits(afe->regmap, cfg->upper_bound_reg, in mt8195_afe_setup_apll_tuner()
240 static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe, in mt8195_afe_enable_tuner_clk() argument
243 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_enable_tuner_clk()
247 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); in mt8195_afe_enable_tuner_clk()
248 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); in mt8195_afe_enable_tuner_clk()
251 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); in mt8195_afe_enable_tuner_clk()
252 mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); in mt8195_afe_enable_tuner_clk()
261 static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe, in mt8195_afe_disable_tuner_clk() argument
264 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_disable_tuner_clk()
268 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); in mt8195_afe_disable_tuner_clk()
269 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); in mt8195_afe_disable_tuner_clk()
272 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); in mt8195_afe_disable_tuner_clk()
273 mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); in mt8195_afe_disable_tuner_clk()
282 static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe, in mt8195_afe_enable_apll_tuner() argument
292 ret = mt8195_afe_setup_apll_tuner(afe, id); in mt8195_afe_enable_apll_tuner()
296 ret = mt8195_afe_enable_tuner_clk(afe, id); in mt8195_afe_enable_apll_tuner()
304 regmap_update_bits(afe->regmap, in mt8195_afe_enable_apll_tuner()
314 static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe, in mt8195_afe_disable_apll_tuner() argument
328 regmap_update_bits(afe->regmap, in mt8195_afe_disable_apll_tuner()
337 ret = mt8195_afe_disable_tuner_clk(afe, id); in mt8195_afe_disable_apll_tuner()
358 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) in mt8195_afe_get_mclk_source_rate() argument
360 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_get_mclk_source_rate()
364 dev_dbg(afe->dev, "invalid clk id\n"); in mt8195_afe_get_mclk_source_rate()
377 int mt8195_afe_init_clock(struct mtk_base_afe *afe) in mt8195_afe_init_clock() argument
379 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_init_clock()
382 mt8195_audsys_clk_register(afe); in mt8195_afe_init_clock()
385 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk), in mt8195_afe_init_clock()
391 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8195_afe_init_clock()
393 dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", in mt8195_afe_init_clock()
404 dev_dbg(afe->dev, "%s(), init apll_tuner%d failed", in mt8195_afe_init_clock()
413 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_enable_clk() argument
420 dev_dbg(afe->dev, "%s(), failed to enable clk\n", in mt8195_afe_enable_clk()
425 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_enable_clk()
431 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_disable_clk() argument
436 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_disable_clk()
440 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_prepare_clk() argument
447 dev_dbg(afe->dev, "%s(), failed to prepare clk\n", in mt8195_afe_prepare_clk()
452 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_prepare_clk()
457 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_unprepare_clk() argument
462 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_unprepare_clk()
465 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_enable_clk_atomic() argument
472 dev_dbg(afe->dev, "%s(), failed to clk enable\n", in mt8195_afe_enable_clk_atomic()
477 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_enable_clk_atomic()
482 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) in mt8195_afe_disable_clk_atomic() argument
487 dev_dbg(afe->dev, "NULL clk\n"); in mt8195_afe_disable_clk_atomic()
490 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, in mt8195_afe_set_clk_rate() argument
498 dev_dbg(afe->dev, "%s(), failed to set clk rate\n", in mt8195_afe_set_clk_rate()
507 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, in mt8195_afe_set_clk_parent() argument
515 dev_dbg(afe->dev, "%s(), failed to set clk parent\n", in mt8195_afe_set_clk_parent()
574 static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) in mt8195_afe_enable_top_cg() argument
580 regmap_update_bits(afe->regmap, reg, mask, val); in mt8195_afe_enable_top_cg()
584 static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) in mt8195_afe_disable_top_cg() argument
590 regmap_update_bits(afe->regmap, reg, mask, val); in mt8195_afe_disable_top_cg()
594 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) in mt8195_afe_enable_reg_rw_clk() argument
596 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_enable_reg_rw_clk()
602 MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */ in mt8195_afe_enable_reg_rw_clk()
604 MT8195_CLK_AUD_AFE, /* AFE HW master switch */ in mt8195_afe_enable_reg_rw_clk()
605 MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/ in mt8195_afe_enable_reg_rw_clk()
606 MT8195_CLK_AUD_A1SYS, /* AFE HW clock */ in mt8195_afe_enable_reg_rw_clk()
610 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_enable_reg_rw_clk()
615 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) in mt8195_afe_disable_reg_rw_clk() argument
617 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_disable_reg_rw_clk()
631 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_disable_reg_rw_clk()
636 static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe) in mt8195_afe_enable_afe_on() argument
638 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); in mt8195_afe_enable_afe_on()
642 static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe) in mt8195_afe_disable_afe_on() argument
644 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); in mt8195_afe_disable_afe_on()
648 static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe) in mt8195_afe_enable_timing_sys() argument
650 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_enable_timing_sys()
663 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_enable_timing_sys()
666 mt8195_afe_enable_top_cg(afe, cg_array[i]); in mt8195_afe_enable_timing_sys()
671 static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe) in mt8195_afe_disable_timing_sys() argument
673 struct mt8195_afe_private *afe_priv = afe->platform_priv; in mt8195_afe_disable_timing_sys()
686 mt8195_afe_disable_top_cg(afe, cg_array[i]); in mt8195_afe_disable_timing_sys()
689 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); in mt8195_afe_disable_timing_sys()
694 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) in mt8195_afe_enable_main_clock() argument
696 mt8195_afe_enable_timing_sys(afe); in mt8195_afe_enable_main_clock()
698 mt8195_afe_enable_afe_on(afe); in mt8195_afe_enable_main_clock()
700 mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1); in mt8195_afe_enable_main_clock()
701 mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2); in mt8195_afe_enable_main_clock()
706 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) in mt8195_afe_disable_main_clock() argument
708 mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2); in mt8195_afe_disable_main_clock()
709 mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1); in mt8195_afe_disable_main_clock()
711 mt8195_afe_disable_afe_on(afe); in mt8195_afe_disable_main_clock()
713 mt8195_afe_disable_timing_sys(afe); in mt8195_afe_disable_main_clock()