17 static const char *aud_clks[CLK_NUM] = {  variable
73 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS],  in mt8192_set_audio_int_bus_parent()
74 			aud_clks[clk_id], ret);  in mt8192_set_audio_int_bus_parent()
89 				__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);  in apll1_mux_setting()
96 				__func__, aud_clks[CLK_TOP_MUX_AUD_1],  in apll1_mux_setting()
97 				aud_clks[CLK_TOP_APLL1_CK], ret);  in apll1_mux_setting()
105 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);  in apll1_mux_setting()
112 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],  in apll1_mux_setting()
113 				aud_clks[CLK_TOP_APLL1_D4], ret);  in apll1_mux_setting()
121 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],  in apll1_mux_setting()
122 				aud_clks[CLK_CLK26M], ret);  in apll1_mux_setting()
131 				__func__, aud_clks[CLK_TOP_MUX_AUD_1],  in apll1_mux_setting()
132 				aud_clks[CLK_CLK26M], ret);  in apll1_mux_setting()
151 				__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);  in apll2_mux_setting()
158 				__func__, aud_clks[CLK_TOP_MUX_AUD_2],  in apll2_mux_setting()
159 				aud_clks[CLK_TOP_APLL2_CK], ret);  in apll2_mux_setting()
167 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);  in apll2_mux_setting()
174 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],  in apll2_mux_setting()
175 				aud_clks[CLK_TOP_APLL2_D4], ret);  in apll2_mux_setting()
183 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],  in apll2_mux_setting()
184 				aud_clks[CLK_CLK26M], ret);  in apll2_mux_setting()
193 				__func__, aud_clks[CLK_TOP_MUX_AUD_2],  in apll2_mux_setting()
194 				aud_clks[CLK_CLK26M], ret);  in apll2_mux_setting()
212 			__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);  in mt8192_afe_enable_clock()
219 			__func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);  in mt8192_afe_enable_clock()
226 			__func__, aud_clks[CLK_MUX_AUDIO], ret);  in mt8192_afe_enable_clock()
233 			__func__, aud_clks[CLK_MUX_AUDIO],  in mt8192_afe_enable_clock()
234 			aud_clks[CLK_CLK26M], ret);  in mt8192_afe_enable_clock()
241 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);  in mt8192_afe_enable_clock()
248 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS],  in mt8192_afe_enable_clock()
249 			aud_clks[CLK_CLK26M], ret);  in mt8192_afe_enable_clock()
257 			__func__, aud_clks[CLK_TOP_MUX_AUDIO_H],  in mt8192_afe_enable_clock()
258 			aud_clks[CLK_TOP_APLL2_CK], ret);  in mt8192_afe_enable_clock()
265 			__func__, aud_clks[CLK_AFE], ret);  in mt8192_afe_enable_clock()
296 			__func__, aud_clks[CLK_APLL22M], ret);  in mt8192_apll1_enable()
303 			__func__, aud_clks[CLK_APLL1_TUNER], ret);  in mt8192_apll1_enable()
346 			__func__, aud_clks[CLK_APLL24M], ret);  in mt8192_apll2_enable()
353 			__func__, aud_clks[CLK_APLL2_TUNER], ret);  in mt8192_apll2_enable()
577 				__func__, aud_clks[m_sel_id], ret);  in mt8192_mck_enable()
584 				__func__, aud_clks[m_sel_id],  in mt8192_mck_enable()
585 				aud_clks[apll_clk_id], ret);  in mt8192_mck_enable()
594 			__func__, aud_clks[div_clk_id], ret);  in mt8192_mck_enable()
600 			__func__, aud_clks[div_clk_id],  in mt8192_mck_enable()
631 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8192_init_clock()
635 				 aud_clks[i], PTR_ERR(afe_priv->clk[i]));  in mt8192_init_clock()