1 // SPDX-License-Identifier: GPL-2.0
3  * mt8188-afe-clk.c  --  MediaTek 8188 afe clock ctrl
8  *         Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
13 #include "mt8188-afe-common.h"
14 #include "mt8188-afe-clk.h"
15 #include "mt8188-audsys-clk.h"
16 #include "mt8188-reg.h"
51 	/* afe clock gate */
218 		return -EINVAL;  in mt8188_afe_init_apll_tuner()
220 	cfg->ref_cnt = 0;  in mt8188_afe_init_apll_tuner()
221 	spin_lock_init(&cfg->ctrl_lock);  in mt8188_afe_init_apll_tuner()
226 static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)  in mt8188_afe_setup_apll_tuner()  argument
231 		return -EINVAL;  in mt8188_afe_setup_apll_tuner()
233 	regmap_update_bits(afe->regmap,  in mt8188_afe_setup_apll_tuner()
234 			   cfg->apll_div_reg,  in mt8188_afe_setup_apll_tuner()
235 			   cfg->apll_div_maskbit << cfg->apll_div_shift,  in mt8188_afe_setup_apll_tuner()
236 			   cfg->apll_div_default << cfg->apll_div_shift);  in mt8188_afe_setup_apll_tuner()
238 	regmap_update_bits(afe->regmap,  in mt8188_afe_setup_apll_tuner()
239 			   cfg->ref_ck_sel_reg,  in mt8188_afe_setup_apll_tuner()
240 			   cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,  in mt8188_afe_setup_apll_tuner()
241 			   cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);  in mt8188_afe_setup_apll_tuner()
243 	regmap_update_bits(afe->regmap,  in mt8188_afe_setup_apll_tuner()
244 			   cfg->upper_bound_reg,  in mt8188_afe_setup_apll_tuner()
245 			   cfg->upper_bound_maskbit << cfg->upper_bound_shift,  in mt8188_afe_setup_apll_tuner()
246 			   cfg->upper_bound_default << cfg->upper_bound_shift);  in mt8188_afe_setup_apll_tuner()
251 static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,  in mt8188_afe_enable_tuner_clk()  argument
254 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_enable_tuner_clk()
258 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);  in mt8188_afe_enable_tuner_clk()
259 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);  in mt8188_afe_enable_tuner_clk()
262 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);  in mt8188_afe_enable_tuner_clk()
263 		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);  in mt8188_afe_enable_tuner_clk()
266 		return -EINVAL;  in mt8188_afe_enable_tuner_clk()
272 static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,  in mt8188_afe_disable_tuner_clk()  argument
275 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_disable_tuner_clk()
279 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);  in mt8188_afe_disable_tuner_clk()
280 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);  in mt8188_afe_disable_tuner_clk()
283 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);  in mt8188_afe_disable_tuner_clk()
284 		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);  in mt8188_afe_disable_tuner_clk()
287 		return -EINVAL;  in mt8188_afe_disable_tuner_clk()
293 static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)  in mt8188_afe_enable_apll_tuner()  argument
300 		return -EINVAL;  in mt8188_afe_enable_apll_tuner()
302 	ret = mt8188_afe_setup_apll_tuner(afe, id);  in mt8188_afe_enable_apll_tuner()
306 	ret = mt8188_afe_enable_tuner_clk(afe, id);  in mt8188_afe_enable_apll_tuner()
310 	spin_lock_irqsave(&cfg->ctrl_lock, flags);  in mt8188_afe_enable_apll_tuner()
312 	cfg->ref_cnt++;  in mt8188_afe_enable_apll_tuner()
313 	if (cfg->ref_cnt == 1)  in mt8188_afe_enable_apll_tuner()
314 		regmap_update_bits(afe->regmap,  in mt8188_afe_enable_apll_tuner()
315 				   cfg->tuner_en_reg,  in mt8188_afe_enable_apll_tuner()
316 				   cfg->tuner_en_maskbit << cfg->tuner_en_shift,  in mt8188_afe_enable_apll_tuner()
317 				   BIT(cfg->tuner_en_shift));  in mt8188_afe_enable_apll_tuner()
319 	spin_unlock_irqrestore(&cfg->ctrl_lock, flags);  in mt8188_afe_enable_apll_tuner()
324 static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)  in mt8188_afe_disable_apll_tuner()  argument
331 		return -EINVAL;  in mt8188_afe_disable_apll_tuner()
333 	spin_lock_irqsave(&cfg->ctrl_lock, flags);  in mt8188_afe_disable_apll_tuner()
335 	cfg->ref_cnt--;  in mt8188_afe_disable_apll_tuner()
336 	if (cfg->ref_cnt == 0)  in mt8188_afe_disable_apll_tuner()
337 		regmap_update_bits(afe->regmap,  in mt8188_afe_disable_apll_tuner()
338 				   cfg->tuner_en_reg,  in mt8188_afe_disable_apll_tuner()
339 				   cfg->tuner_en_maskbit << cfg->tuner_en_shift,  in mt8188_afe_disable_apll_tuner()
340 				   0 << cfg->tuner_en_shift);  in mt8188_afe_disable_apll_tuner()
341 	else if (cfg->ref_cnt < 0)  in mt8188_afe_disable_apll_tuner()
342 		cfg->ref_cnt = 0;  in mt8188_afe_disable_apll_tuner()
344 	spin_unlock_irqrestore(&cfg->ctrl_lock, flags);  in mt8188_afe_disable_apll_tuner()
346 	ret = mt8188_afe_disable_tuner_clk(afe, id);  in mt8188_afe_disable_apll_tuner()
363 		return -EINVAL;  in mt8188_afe_get_mclk_source_clk_id()
367 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)  in mt8188_afe_get_mclk_source_rate()  argument
369 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_get_mclk_source_rate()
373 		dev_dbg(afe->dev, "invalid clk id\n");  in mt8188_afe_get_mclk_source_rate()
377 	return clk_get_rate(afe_priv->clk[clk_id]);  in mt8188_afe_get_mclk_source_rate()
386 int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)  in mt8188_get_apll_by_rate()  argument
391 int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)  in mt8188_get_apll_by_name()  argument
399 int mt8188_afe_init_clock(struct mtk_base_afe *afe)  in mt8188_afe_init_clock()  argument
401 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_init_clock()
404 	ret = mt8188_audsys_clk_register(afe);  in mt8188_afe_init_clock()
406 		dev_err(afe->dev, "register audsys clk fail %d\n", ret);  in mt8188_afe_init_clock()
410 	afe_priv->clk =  in mt8188_afe_init_clock()
411 		devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),  in mt8188_afe_init_clock()
413 	if (!afe_priv->clk)  in mt8188_afe_init_clock()
414 		return -ENOMEM;  in mt8188_afe_init_clock()
417 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8188_afe_init_clock()
418 		if (IS_ERR(afe_priv->clk[i])) {  in mt8188_afe_init_clock()
419 			dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",  in mt8188_afe_init_clock()
421 				PTR_ERR(afe_priv->clk[i]));  in mt8188_afe_init_clock()
422 			return PTR_ERR(afe_priv->clk[i]);  in mt8188_afe_init_clock()
430 			dev_info(afe->dev, "%s(), init apll_tuner%d failed",  in mt8188_afe_init_clock()
432 			return -EINVAL;  in mt8188_afe_init_clock()
439 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)  in mt8188_afe_enable_clk()  argument
446 			dev_dbg(afe->dev, "%s(), failed to enable clk\n",  in mt8188_afe_enable_clk()
451 		dev_dbg(afe->dev, "NULL clk\n");  in mt8188_afe_enable_clk()
457 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)  in mt8188_afe_disable_clk()  argument
462 		dev_dbg(afe->dev, "NULL clk\n");  in mt8188_afe_disable_clk()
466 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,  in mt8188_afe_set_clk_rate()  argument
474 			dev_dbg(afe->dev, "%s(), failed to set clk rate\n",  in mt8188_afe_set_clk_rate()
483 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,  in mt8188_afe_set_clk_parent()  argument
491 			dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",  in mt8188_afe_set_clk_parent()
550 static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)  in mt8188_afe_enable_top_cg()  argument
556 	regmap_update_bits(afe->regmap, reg, mask, val);  in mt8188_afe_enable_top_cg()
561 static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)  in mt8188_afe_disable_top_cg()  argument
567 	regmap_update_bits(afe->regmap, reg, mask, val);  in mt8188_afe_disable_top_cg()
572 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)  in mt8188_afe_enable_reg_rw_clk()  argument
574 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_enable_reg_rw_clk()
576 	/* bus clock for AFE external access, like DRAM */  in mt8188_afe_enable_reg_rw_clk()
577 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);  in mt8188_afe_enable_reg_rw_clk()
579 	/* bus clock for AFE internal access, like AFE SRAM */  in mt8188_afe_enable_reg_rw_clk()
580 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);  in mt8188_afe_enable_reg_rw_clk()
583 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);  in mt8188_afe_enable_reg_rw_clk()
585 	/* AFE hw clock */  in mt8188_afe_enable_reg_rw_clk()
586 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);  in mt8188_afe_enable_reg_rw_clk()
587 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);  in mt8188_afe_enable_reg_rw_clk()
588 	mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);  in mt8188_afe_enable_reg_rw_clk()
593 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)  in mt8188_afe_disable_reg_rw_clk()  argument
595 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_disable_reg_rw_clk()
597 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);  in mt8188_afe_disable_reg_rw_clk()
598 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);  in mt8188_afe_disable_reg_rw_clk()
599 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);  in mt8188_afe_disable_reg_rw_clk()
600 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);  in mt8188_afe_disable_reg_rw_clk()
601 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);  in mt8188_afe_disable_reg_rw_clk()
602 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);  in mt8188_afe_disable_reg_rw_clk()
607 static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)  in mt8188_afe_enable_afe_on()  argument
609 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);  in mt8188_afe_enable_afe_on()
613 static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)  in mt8188_afe_disable_afe_on()  argument
615 	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);  in mt8188_afe_disable_afe_on()
619 static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)  in mt8188_afe_enable_a1sys()  argument
621 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_enable_a1sys()
624 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);  in mt8188_afe_enable_a1sys()
628 	return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);  in mt8188_afe_enable_a1sys()
631 static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)  in mt8188_afe_disable_a1sys()  argument
633 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_disable_a1sys()
635 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);  in mt8188_afe_disable_a1sys()
636 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);  in mt8188_afe_disable_a1sys()
640 static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)  in mt8188_afe_enable_a2sys()  argument
642 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_enable_a2sys()
645 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);  in mt8188_afe_enable_a2sys()
649 	return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);  in mt8188_afe_enable_a2sys()
652 static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)  in mt8188_afe_disable_a2sys()  argument
654 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_afe_disable_a2sys()
656 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);  in mt8188_afe_disable_a2sys()
657 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);  in mt8188_afe_disable_a2sys()
661 int mt8188_apll1_enable(struct mtk_base_afe *afe)  in mt8188_apll1_enable()  argument
663 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_apll1_enable()
666 	ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);  in mt8188_apll1_enable()
670 	ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],  in mt8188_apll1_enable()
671 					afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);  in mt8188_apll1_enable()
675 	ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);  in mt8188_apll1_enable()
679 	ret = mt8188_afe_enable_a1sys(afe);  in mt8188_apll1_enable()
686 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);  in mt8188_apll1_enable()
688 	mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],  in mt8188_apll1_enable()
689 				  afe_priv->clk[MT8188_CLK_XTAL_26M]);  in mt8188_apll1_enable()
691 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);  in mt8188_apll1_enable()
696 int mt8188_apll1_disable(struct mtk_base_afe *afe)  in mt8188_apll1_disable()  argument
698 	struct mt8188_afe_private *afe_priv = afe->platform_priv;  in mt8188_apll1_disable()
700 	mt8188_afe_disable_a1sys(afe);  in mt8188_apll1_disable()
701 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);  in mt8188_apll1_disable()
702 	mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],  in mt8188_apll1_disable()
703 				  afe_priv->clk[MT8188_CLK_XTAL_26M]);  in mt8188_apll1_disable()
704 	mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);  in mt8188_apll1_disable()
709 int mt8188_apll2_enable(struct mtk_base_afe *afe)  in mt8188_apll2_enable()  argument
713 	ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);  in mt8188_apll2_enable()
717 	ret =  mt8188_afe_enable_a2sys(afe);  in mt8188_apll2_enable()
723 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);  in mt8188_apll2_enable()
728 int mt8188_apll2_disable(struct mtk_base_afe *afe)  in mt8188_apll2_disable()  argument
730 	mt8188_afe_disable_a2sys(afe);  in mt8188_apll2_disable()
731 	mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);  in mt8188_apll2_disable()
735 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)  in mt8188_afe_enable_main_clock()  argument
737 	mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);  in mt8188_afe_enable_main_clock()
738 	mt8188_afe_enable_afe_on(afe);  in mt8188_afe_enable_main_clock()
742 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)  in mt8188_afe_disable_main_clock()  argument
744 	mt8188_afe_disable_afe_on(afe);  in mt8188_afe_disable_main_clock()
745 	mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);  in mt8188_afe_disable_main_clock()