Lines Matching +full:mt8186 +full:- +full:topckgen
1 // SPDX-License-Identifier: GPL-2.0
3 // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-clk.h"
14 #include "mt8186-audsys-clk.h"
76 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_set_audio_int_bus_parent()
79 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8186_set_audio_int_bus_parent()
80 afe_priv->clk[clk_id]); in mt8186_set_audio_int_bus_parent()
82 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_set_audio_int_bus_parent()
93 struct mt8186_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
97 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
99 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll1_mux_setting()
103 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
104 afe_priv->clk[CLK_TOP_APLL1_CK]); in apll1_mux_setting()
106 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
113 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
115 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll1_mux_setting()
119 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
120 afe_priv->clk[CLK_TOP_APLL1_D8]); in apll1_mux_setting()
122 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
128 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
129 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
131 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
136 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]); in apll1_mux_setting()
138 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
139 afe_priv->clk[CLK_CLK26M]); in apll1_mux_setting()
141 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
146 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
154 struct mt8186_afe_private *afe_priv = afe->platform_priv; in apll2_mux_setting()
158 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
160 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll2_mux_setting()
164 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
165 afe_priv->clk[CLK_TOP_APLL2_CK]); in apll2_mux_setting()
167 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
174 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); in apll2_mux_setting()
176 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll2_mux_setting()
180 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
181 afe_priv->clk[CLK_TOP_APLL2_D8]); in apll2_mux_setting()
183 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
190 afe_priv->clk[CLK_CLK26M]); in apll2_mux_setting()
192 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
197 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]); in apll2_mux_setting()
199 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
200 afe_priv->clk[CLK_CLK26M]); in apll2_mux_setting()
202 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
207 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]); in apll2_mux_setting()
215 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_enable_cgs()
220 ret = clk_prepare_enable(afe_priv->clk[i]); in mt8186_afe_enable_cgs()
222 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_cgs()
233 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_disable_cgs()
237 clk_disable_unprepare(afe_priv->clk[i]); in mt8186_afe_disable_cgs()
242 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_enable_clock()
245 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8186_afe_enable_clock()
247 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
252 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]); in mt8186_afe_enable_clock()
254 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
259 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]); in mt8186_afe_enable_clock()
261 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
265 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8186_afe_enable_clock()
266 afe_priv->clk[CLK_CLK26M]); in mt8186_afe_enable_clock()
268 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_afe_enable_clock()
274 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_enable_clock()
276 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
285 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H], in mt8186_afe_enable_clock()
286 afe_priv->clk[CLK_TOP_APLL2_CK]); in mt8186_afe_enable_clock()
288 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_afe_enable_clock()
294 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]); in mt8186_afe_enable_clock()
296 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
304 clk_disable_unprepare(afe_priv->clk[CLK_AFE]); in mt8186_afe_enable_clock()
309 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_enable_clock()
311 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); in mt8186_afe_enable_clock()
313 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8186_afe_enable_clock()
315 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]); in mt8186_afe_enable_clock()
322 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_disable_clock()
324 clk_disable_unprepare(afe_priv->clk[CLK_AFE]); in mt8186_afe_disable_clock()
326 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_disable_clock()
327 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]); in mt8186_afe_disable_clock()
328 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]); in mt8186_afe_disable_clock()
329 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]); in mt8186_afe_disable_clock()
334 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_suspend_clock()
338 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_suspend_clock()
340 dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_suspend_clock()
348 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_suspend_clock()
355 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_suspend_clock()
361 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_resume_clock()
365 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_resume_clock()
367 dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_resume_clock()
376 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_resume_clock()
383 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]); in mt8186_afe_resume_clock()
389 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll1_enable()
395 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]); in mt8186_apll1_enable()
397 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll1_enable()
402 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]); in mt8186_apll1_enable()
404 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll1_enable()
409 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832); in mt8186_apll1_enable()
410 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1); in mt8186_apll1_enable()
412 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll1_enable()
418 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); in mt8186_apll1_enable()
420 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); in mt8186_apll1_enable()
427 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll1_disable()
429 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll1_disable()
432 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0); in mt8186_apll1_disable()
434 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]); in mt8186_apll1_disable()
435 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]); in mt8186_apll1_disable()
442 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll2_enable()
448 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]); in mt8186_apll2_enable()
450 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll2_enable()
455 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]); in mt8186_apll2_enable()
457 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll2_enable()
462 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634); in mt8186_apll2_enable()
463 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1); in mt8186_apll2_enable()
465 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll2_enable()
471 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); in mt8186_apll2_enable()
473 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); in mt8186_apll2_enable()
480 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll2_disable()
482 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll2_disable()
485 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0); in mt8186_apll2_disable()
487 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]); in mt8186_apll2_disable()
488 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]); in mt8186_apll2_disable()
542 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_mck_enable()
552 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]); in mt8186_mck_enable()
554 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", in mt8186_mck_enable()
558 ret = clk_set_parent(afe_priv->clk[m_sel_id], in mt8186_mck_enable()
559 afe_priv->clk[apll_clk_id]); in mt8186_mck_enable()
561 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", in mt8186_mck_enable()
569 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]); in mt8186_mck_enable()
571 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", in mt8186_mck_enable()
575 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate); in mt8186_mck_enable()
577 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n", in mt8186_mck_enable()
587 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_mck_disable()
591 clk_disable_unprepare(afe_priv->clk[div_clk_id]); in mt8186_mck_disable()
593 clk_disable_unprepare(afe_priv->clk[m_sel_id]); in mt8186_mck_disable()
598 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_init_clock()
599 struct device_node *of_node = afe->dev->of_node; in mt8186_init_clock()
604 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt8186_init_clock()
606 if (!afe_priv->clk) in mt8186_init_clock()
607 return -ENOMEM; in mt8186_init_clock()
610 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8186_init_clock()
611 if (IS_ERR(afe_priv->clk[i])) { in mt8186_init_clock()
612 dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n", in mt8186_init_clock()
614 aud_clks[i], PTR_ERR(afe_priv->clk[i])); in mt8186_init_clock()
615 afe_priv->clk[i] = NULL; in mt8186_init_clock()
619 afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node, in mt8186_init_clock()
621 if (IS_ERR(afe_priv->apmixedsys)) { in mt8186_init_clock()
622 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n", in mt8186_init_clock()
623 __func__, PTR_ERR(afe_priv->apmixedsys)); in mt8186_init_clock()
624 return PTR_ERR(afe_priv->apmixedsys); in mt8186_init_clock()
627 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node, in mt8186_init_clock()
628 "mediatek,topckgen"); in mt8186_init_clock()
629 if (IS_ERR(afe_priv->topckgen)) { in mt8186_init_clock()
630 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n", in mt8186_init_clock()
631 __func__, PTR_ERR(afe_priv->topckgen)); in mt8186_init_clock()
632 return PTR_ERR(afe_priv->topckgen); in mt8186_init_clock()
635 afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node, in mt8186_init_clock()
637 if (IS_ERR(afe_priv->infracfg)) { in mt8186_init_clock()
638 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n", in mt8186_init_clock()
639 __func__, PTR_ERR(afe_priv->infracfg)); in mt8186_init_clock()
640 return PTR_ERR(afe_priv->infracfg); in mt8186_init_clock()