Lines Matching full:afe
3 // mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-clk.h"
73 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe, in mt8186_set_audio_int_bus_parent() argument
76 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_set_audio_int_bus_parent()
82 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_set_audio_int_bus_parent()
91 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable) in apll1_mux_setting() argument
93 struct mt8186_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
99 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll1_mux_setting()
106 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
115 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll1_mux_setting()
122 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
131 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
141 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
152 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable) in apll2_mux_setting() argument
154 struct mt8186_afe_private *afe_priv = afe->platform_priv; in apll2_mux_setting()
160 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll2_mux_setting()
167 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
176 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll2_mux_setting()
183 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
192 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
202 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
213 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe) in mt8186_afe_enable_cgs() argument
215 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_enable_cgs()
222 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_cgs()
231 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe) in mt8186_afe_disable_cgs() argument
233 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_disable_cgs()
240 int mt8186_afe_enable_clock(struct mtk_base_afe *afe) in mt8186_afe_enable_clock() argument
242 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_enable_clock()
247 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
254 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
261 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
268 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_afe_enable_clock()
276 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
280 ret = mt8186_set_audio_int_bus_parent(afe, in mt8186_afe_enable_clock()
288 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8186_afe_enable_clock()
296 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_enable_clock()
307 mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); in mt8186_afe_enable_clock()
320 void mt8186_afe_disable_clock(struct mtk_base_afe *afe) in mt8186_afe_disable_clock() argument
322 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_disable_clock()
325 mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); in mt8186_afe_disable_clock()
332 int mt8186_afe_suspend_clock(struct mtk_base_afe *afe) in mt8186_afe_suspend_clock() argument
334 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_suspend_clock()
340 dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_suspend_clock()
344 ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); in mt8186_afe_suspend_clock()
353 mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4); in mt8186_afe_suspend_clock()
359 int mt8186_afe_resume_clock(struct mtk_base_afe *afe) in mt8186_afe_resume_clock() argument
361 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_afe_resume_clock()
367 dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_afe_resume_clock()
371 ret = mt8186_set_audio_int_bus_parent(afe, in mt8186_afe_resume_clock()
381 mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M); in mt8186_afe_resume_clock()
387 int mt8186_apll1_enable(struct mtk_base_afe *afe) in mt8186_apll1_enable() argument
389 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll1_enable()
393 apll1_mux_setting(afe, true); in mt8186_apll1_enable()
397 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll1_enable()
404 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll1_enable()
409 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832); in mt8186_apll1_enable()
410 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1); in mt8186_apll1_enable()
412 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll1_enable()
425 void mt8186_apll1_disable(struct mtk_base_afe *afe) in mt8186_apll1_disable() argument
427 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll1_disable()
429 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll1_disable()
432 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0); in mt8186_apll1_disable()
437 apll1_mux_setting(afe, false); in mt8186_apll1_disable()
440 int mt8186_apll2_enable(struct mtk_base_afe *afe) in mt8186_apll2_enable() argument
442 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll2_enable()
446 apll2_mux_setting(afe, true); in mt8186_apll2_enable()
450 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll2_enable()
457 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8186_apll2_enable()
462 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634); in mt8186_apll2_enable()
463 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1); in mt8186_apll2_enable()
465 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll2_enable()
478 void mt8186_apll2_disable(struct mtk_base_afe *afe) in mt8186_apll2_disable() argument
480 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_apll2_disable()
482 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8186_apll2_disable()
485 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0); in mt8186_apll2_disable()
490 apll2_mux_setting(afe, false); in mt8186_apll2_disable()
493 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8186_get_apll_rate() argument
498 int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate) in mt8186_get_apll_by_rate() argument
503 int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name) in mt8186_get_apll_by_name() argument
540 int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) in mt8186_mck_enable() argument
542 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_mck_enable()
543 int apll = mt8186_get_apll_by_rate(afe, rate); in mt8186_mck_enable()
554 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", in mt8186_mck_enable()
561 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", in mt8186_mck_enable()
571 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", in mt8186_mck_enable()
577 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n", in mt8186_mck_enable()
585 void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id) in mt8186_mck_disable() argument
587 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_mck_disable()
596 int mt8186_init_clock(struct mtk_base_afe *afe) in mt8186_init_clock() argument
598 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_init_clock()
599 struct device_node *of_node = afe->dev->of_node; in mt8186_init_clock()
602 mt8186_audsys_clk_register(afe); in mt8186_init_clock()
604 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt8186_init_clock()
610 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8186_init_clock()
612 dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n", in mt8186_init_clock()
622 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n", in mt8186_init_clock()
630 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n", in mt8186_init_clock()
638 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n", in mt8186_init_clock()