54 static const char *aud_clks[CLK_NUM] = {  variable
103 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8183_init_clock()
106 				__func__, aud_clks[i],  in mt8183_init_clock()
123 			__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);  in mt8183_afe_enable_clock()
130 			__func__, aud_clks[CLK_MUX_AUDIO], ret);  in mt8183_afe_enable_clock()
138 			__func__, aud_clks[CLK_MUX_AUDIO],  in mt8183_afe_enable_clock()
139 			aud_clks[CLK_CLK26M], ret);  in mt8183_afe_enable_clock()
146 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);  in mt8183_afe_enable_clock()
154 			__func__, aud_clks[CLK_MUX_AUDIOINTBUS],  in mt8183_afe_enable_clock()
155 			aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);  in mt8183_afe_enable_clock()
162 			__func__, aud_clks[CLK_AFE], ret);  in mt8183_afe_enable_clock()
169 			__func__, aud_clks[CLK_I2S1_BCLK_SW], ret);  in mt8183_afe_enable_clock()
176 			__func__, aud_clks[CLK_I2S2_BCLK_SW], ret);  in mt8183_afe_enable_clock()
183 			__func__, aud_clks[CLK_I2S3_BCLK_SW], ret);  in mt8183_afe_enable_clock()
190 			__func__, aud_clks[CLK_I2S4_BCLK_SW], ret);  in mt8183_afe_enable_clock()
240 				__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);  in apll1_mux_setting()
247 				__func__, aud_clks[CLK_TOP_MUX_AUD_1],  in apll1_mux_setting()
248 				aud_clks[CLK_TOP_APLL1_CK], ret);  in apll1_mux_setting()
256 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);  in apll1_mux_setting()
263 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],  in apll1_mux_setting()
264 				aud_clks[CLK_TOP_APLL1_D8], ret);  in apll1_mux_setting()
272 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],  in apll1_mux_setting()
273 				aud_clks[CLK_CLK26M], ret);  in apll1_mux_setting()
282 				__func__, aud_clks[CLK_TOP_MUX_AUD_1],  in apll1_mux_setting()
283 				aud_clks[CLK_CLK26M], ret);  in apll1_mux_setting()
314 				__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);  in apll2_mux_setting()
321 				__func__, aud_clks[CLK_TOP_MUX_AUD_2],  in apll2_mux_setting()
322 				aud_clks[CLK_TOP_APLL2_CK], ret);  in apll2_mux_setting()
330 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);  in apll2_mux_setting()
337 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],  in apll2_mux_setting()
338 				aud_clks[CLK_TOP_APLL2_D8], ret);  in apll2_mux_setting()
346 				__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],  in apll2_mux_setting()
347 				aud_clks[CLK_CLK26M], ret);  in apll2_mux_setting()
356 				__func__, aud_clks[CLK_TOP_MUX_AUD_2],  in apll2_mux_setting()
357 				aud_clks[CLK_CLK26M], ret);  in apll2_mux_setting()
390 			__func__, aud_clks[CLK_APLL22M], ret);  in mt8183_apll1_enable()
397 			__func__, aud_clks[CLK_APLL1_TUNER], ret);  in mt8183_apll1_enable()
444 			__func__, aud_clks[CLK_APLL24M], ret);  in mt8183_apll2_enable()
451 			__func__, aud_clks[CLK_APLL2_TUNER], ret);  in mt8183_apll2_enable()
561 				__func__, aud_clks[m_sel_id], ret);  in mt8183_mck_enable()
568 				__func__, aud_clks[m_sel_id],  in mt8183_mck_enable()
569 				aud_clks[apll_clk_id], ret);  in mt8183_mck_enable()
578 			__func__, aud_clks[div_clk_id], ret);  in mt8183_mck_enable()
584 			__func__, aud_clks[div_clk_id],  in mt8183_mck_enable()