Lines Matching +full:12 +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * mt7986-reg.h  --  MediaTek 7986 audio driver reg definition
75 #define CLK_OUT5_PDN                    BIT(14)
76 #define CLK_OUT5_PDN_MASK               BIT(14)
77 #define CLK_IN5_PDN                     BIT(7)
78 #define CLK_IN5_PDN_MASK                BIT(7)
81 #define PDN_APLL_TUNER2                 BIT(12)
82 #define PDN_APLL_TUNER2_MASK            BIT(12)
85 #define AUD_APLL2_EN                    BIT(3)
86 #define AUD_APLL2_EN_MASK               BIT(3)
87 #define AUD_26M_EN                      BIT(0)
88 #define AUD_26M_EN_MASK                 BIT(0)
93 #define DL0_ON_MASK_SFT                 BIT(28)
105 #define DL0_MONO_MASK_SFT               BIT(4)
108 #define DL0_HALIGN_MASK_SFT             BIT(2)
116 #define VUL0_ON_MASK_SFT                BIT(28)
122 #define VUL0_MONO_MASK_SFT              BIT(4)
125 #define VUL0_HALIGN_MASK_SFT            BIT(2)
136 #define IRQ_MCU_ON_MASK_SFT             BIT(0)
139 #define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
142 #define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
145 #define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
150 #define IN_CLK_SRC_MASK                 GENMASK(12, 10)
161 #define IN_CLK_INV                      BIT(18)
162 #define IN_CLK_INV_MASK                 BIT(18)
170 #define ETDM_SYNC                       BIT(1)
171 #define ETDM_SYNC_MASK                  BIT(1)
172 #define ETDM_EN                         BIT(0)
173 #define ETDM_EN_MASK                    BIT(0)
187 #define ETDM_CLK_DIV                    BIT(12)
188 #define ETDM_CLK_DIV_MASK               BIT(12)
189 #define OUT_CLK_INV                     BIT(9)
190 #define OUT_CLK_INV_MASK                BIT(9)
193 #define OUT_SEL(x)                      ((x) << 12)
194 #define OUT_SEL_SFT                     12
195 #define OUT_SEL_MASK                    GENMASK(15, 12)