133 #define catpt_num_dram(cdev)	(hweight_long((cdev)->spec->dram_mask))  argument
134 #define catpt_num_iram(cdev)	(hweight_long((cdev)->spec->iram_mask))  argument
135 #define catpt_dram_size(cdev)	(catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE)  argument
136 #define catpt_iram_size(cdev)	(catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE)  argument
140 #define catpt_shim_addr(cdev) \  argument
141 	((cdev)->lpe_ba + (cdev)->spec->host_shim_offset)
142 #define catpt_dma_addr(cdev, dma) \  argument
143 	((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma])
144 #define catpt_ssp_addr(cdev, ssp) \  argument
145 	((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp])
146 #define catpt_inbox_addr(cdev) \  argument
147 	((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset)
148 #define catpt_outbox_addr(cdev) \  argument
149 	((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset)
151 #define catpt_writel_ssp(cdev, ssp, reg, val) \  argument
152 	writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
154 #define catpt_readl_shim(cdev, reg) \  argument
155 	readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
156 #define catpt_writel_shim(cdev, reg, val) \  argument
157 	writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
158 #define catpt_updatel_shim(cdev, reg, mask, val) \  argument
159 	catpt_writel_shim(cdev, reg, \
160 			  (catpt_readl_shim(cdev, reg) & ~(mask)) | (val))
162 #define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \  argument
163 	readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_##reg, \
166 #define catpt_readl_pci(cdev, reg) \  argument
167 	readl(cdev->pci_ba + CATPT_PCI_##reg)
168 #define catpt_writel_pci(cdev, reg, val) \  argument
169 	writel(val, cdev->pci_ba + CATPT_PCI_##reg)
170 #define catpt_updatel_pci(cdev, reg, mask, val) \  argument
171 	catpt_writel_pci(cdev, reg, \
172 			 (catpt_readl_pci(cdev, reg) & ~(mask)) | (val))
174 #define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \  argument
175 	readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_##reg, \