Lines Matching +full:3 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
17 #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK 3
19 #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK 3
21 #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK 3
23 #define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK 3
25 #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK 3
27 #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK 3
29 #define HII2S_SW_RST_N__SW_RST_N BIT(0)
41 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
42 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
43 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
44 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
45 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
46 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
47 #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13)
48 #define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN BIT(12)
49 #define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN BIT(10)
50 #define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN BIT(9)
51 #define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN BIT(8)
52 #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN BIT(7)
53 #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN BIT(6)
54 #define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN BIT(5)
55 #define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN BIT(4)
56 #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN BIT(3)
57 #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN BIT(2)
58 #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN BIT(1)
59 #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN BIT(0)
62 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN BIT(30)
63 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN BIT(28)
64 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN BIT(25)
65 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN BIT(24)
66 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN BIT(22)
67 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN BIT(20)
68 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN BIT(17)
69 #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN BIT(16)
99 #define HII2S_I2S_CFG__S2_IF_TX_EN BIT(31)
100 #define HII2S_I2S_CFG__S2_IF_RX_EN BIT(30)
101 #define HII2S_I2S_CFG__S2_FRAME_MODE BIT(29)
102 #define HII2S_I2S_CFG__S2_MST_SLV BIT(28)
103 #define HII2S_I2S_CFG__S2_LRCK_MODE BIT(27)
104 #define HII2S_I2S_CFG__S2_CHNNL_MODE BIT(26)
106 #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK 3
108 #define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK 3
109 #define HII2S_I2S_CFG__S2_TX_CLK_SEL BIT(21)
110 #define HII2S_I2S_CFG__S2_RX_CLK_SEL BIT(20)
111 #define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT BIT(19)
114 #define HII2S_I2S_CFG__S1_IF_TX_EN BIT(15)
115 #define HII2S_I2S_CFG__S1_IF_RX_EN BIT(14)
116 #define HII2S_I2S_CFG__S1_FRAME_MODE BIT(13)
117 #define HII2S_I2S_CFG__S1_MST_SLV BIT(12)
118 #define HII2S_I2S_CFG__S1_LRCK_MODE BIT(11)
119 #define HII2S_I2S_CFG__S1_CHNNL_MODE BIT(10)
121 #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK 3
123 #define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK 3
124 #define HII2S_I2S_CFG__S1_TX_CLK_SEL BIT(5)
125 #define HII2S_I2S_CFG__S1_RX_CLK_SEL BIT(4)
126 #define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT BIT(3)
141 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK 3
142 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE BIT(27)
143 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE BIT(26)
144 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE BIT(25)
145 #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE BIT(24)
147 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK 3
148 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE BIT(19)
149 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE BIT(18)
150 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE BIT(17)
151 #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE BIT(16)
152 #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER BIT(9)
153 #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER BIT(8)
168 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK 3
169 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE BIT(13)
170 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE BIT(12)
172 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK 3
173 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE BIT(9)
174 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE BIT(8)
175 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY BIT(6)
177 #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK 3
178 #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY BIT(3)
225 #define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL BIT(17)
226 #define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL BIT(16)
227 #define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL BIT(14)
228 #define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL BIT(13)
229 #define HII2S_MISC_CFG__S3_DIN_TEST_SEL BIT(12)
230 #define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL BIT(8)
231 #define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL BIT(7)
232 #define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL BIT(6)
233 #define HII2S_MISC_CFG__ST_DL_TEST_SEL BIT(4)
234 #define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL BIT(3)
235 #define HII2S_MISC_CFG__S2_DOUT_TEST_SEL BIT(2)
236 #define HII2S_MISC_CFG__S1_DOUT_TEST_SEL BIT(1)
237 #define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL BIT(0)
251 #define HII2S_CLK_SEL__I2S_BT_FM_SEL BIT(0)
253 #define HII2S_CLK_SEL__EXT_12_288MHZ_SEL BIT(1)