Lines Matching +full:0 +full:x70000

31 #define LPC3XXX_REG_I2S_DAO		0x00
32 #define LPC3XXX_REG_I2S_DAI		0x04
33 #define LPC3XXX_REG_I2S_TX_FIFO	0x08
34 #define LPC3XXX_REG_I2S_RX_FIFO	0x0C
35 #define LPC3XXX_REG_I2S_STAT	0x10
36 #define LPC3XXX_REG_I2S_DMA0	0x14
37 #define LPC3XXX_REG_I2S_DMA1	0x18
38 #define LPC3XXX_REG_I2S_IRQ		0x1C
39 #define LPC3XXX_REG_I2S_TX_RATE	0x20
40 #define LPC3XXX_REG_I2S_RX_RATE	0x24
43 #define LPC3XXX_I2S_WW8      FIELD_PREP(0x3, 0) /* Word width is 8bit */
44 #define LPC3XXX_I2S_WW16     FIELD_PREP(0x3, 1) /* Word width is 16bit */
45 #define LPC3XXX_I2S_WW32     FIELD_PREP(0x3, 3) /* Word width is 32bit */
49 #define LPC3XXX_I2S_WS_SEL   BIT(5)   /* Channel Master(0) or slave(1) mode select */
50 #define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
53 #define LPC3XXX_I2S_WW32_HP  0x1f /* Word select half period for 32bit word width */
54 #define LPC3XXX_I2S_WW16_HP  0x0f /* Word select half period for 16bit word width */
55 #define LPC3XXX_I2S_WW8_HP   0x7  /* Word select half period for 8bit word width */
58 #define LPC3XXX_I2S_IRQ_STAT     BIT(0)
63 #define LPC3XXX_I2S_DMA0_RX_EN     BIT(0)       /* Enable RX DMA1 */
65 #define LPC3XXX_I2S_DMA0_RX_DEPTH(s) FIELD_PREP(0xF00, s)  /* Set the DMA1 RX Request level */
66 #define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA1 TX Request level */
69 #define LPC3XXX_I2S_DMA1_RX_EN     BIT(0)       /* Enable RX DMA1 */
71 #define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 RX Request level */
72 #define LPC3XXX_I2S_DMA1_TX_DEPTH(s) FIELD_PREP(0x70000, s) /* Set the DMA1 TX Request level */
75 #define LPC3XXX_I2S_RX_IRQ_EN     BIT(0)       /* Enable RX IRQ */
77 #define LPC3XXX_I2S_IRQ_RX_DEPTH(s)  FIELD_PREP(0xFF00, s)  /* valid values ar 0 to 7 */
78 #define LPC3XXX_I2S_IRQ_TX_DEPTH(s)  FIELD_PREP(0xFF0000, s) /* valid values ar 0 to 7 */