Lines Matching +full:0 +full:xc000000
11 #define FSL_XCVR_MODE_SPDIF 0
16 #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */
17 #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */
23 #define FSL_XCVR_RX_FIFO_ADDR 0x0C00
24 #define FSL_XCVR_TX_FIFO_ADDR 0x0E00
26 #define FSL_XCVR_VERSION 0x00 /* Version */
27 #define FSL_XCVR_EXT_CTRL 0x10 /* Control */
28 #define FSL_XCVR_EXT_STATUS 0x20 /* Status */
29 #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */
30 #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */
31 #define FSL_XCVR_EXT_ISR 0x50 /* Interrupt status */
32 #define FSL_XCVR_EXT_ISR_SET 0x54 /* Interrupt status */
33 #define FSL_XCVR_EXT_ISR_CLR 0x58 /* Interrupt status */
34 #define FSL_XCVR_EXT_ISR_TOG 0x5C /* Interrupt status */
35 #define FSL_XCVR_IER 0x70 /* Interrupt en for M0+ */
36 #define FSL_XCVR_ISR 0x80 /* Interrupt status */
37 #define FSL_XCVR_ISR_SET 0x84 /* Interrupt status set */
38 #define FSL_XCVR_ISR_CLR 0x88 /* Interrupt status clear */
39 #define FSL_XCVR_ISR_TOG 0x8C /* Interrupt status toggle */
40 #define FSL_XCVR_PHY_AI_CTRL 0x90
41 #define FSL_XCVR_PHY_AI_CTRL_SET 0x94
42 #define FSL_XCVR_PHY_AI_CTRL_CLR 0x98
43 #define FSL_XCVR_PHY_AI_CTRL_TOG 0x9C
44 #define FSL_XCVR_PHY_AI_WDATA 0xA0
45 #define FSL_XCVR_PHY_AI_RDATA 0xA4
46 #define FSL_XCVR_CLK_CTRL 0xB0
47 #define FSL_XCVR_RX_DPTH_CTRL 0x180 /* RX datapath ctrl reg */
48 #define FSL_XCVR_RX_DPTH_CTRL_SET 0x184
49 #define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188
50 #define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c
52 #define FSL_XCVR_RX_CS_DATA_0 0x190
53 #define FSL_XCVR_RX_CS_DATA_1 0x194
54 #define FSL_XCVR_RX_CS_DATA_2 0x198
55 #define FSL_XCVR_RX_CS_DATA_3 0x19C
56 #define FSL_XCVR_RX_CS_DATA_4 0x1A0
57 #define FSL_XCVR_RX_CS_DATA_5 0x1A4
59 #define FSL_XCVR_RX_DPTH_CNTR_CTRL 0x1C0
60 #define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET 0x1C4
61 #define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR 0x1C8
62 #define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG 0x1CC
64 #define FSL_XCVR_RX_DPTH_TSCR 0x1D0
65 #define FSL_XCVR_RX_DPTH_BCR 0x1D4
66 #define FSL_XCVR_RX_DPTH_BCTR 0x1D8
67 #define FSL_XCVR_RX_DPTH_BCRR 0x1DC
69 #define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */
70 #define FSL_XCVR_TX_DPTH_CTRL_SET 0x224
71 #define FSL_XCVR_TX_DPTH_CTRL_CLR 0x228
72 #define FSL_XCVR_TX_DPTH_CTRL_TOG 0x22C
73 #define FSL_XCVR_TX_CS_DATA_0 0x230 /* TX channel status bits regs */
74 #define FSL_XCVR_TX_CS_DATA_1 0x234
75 #define FSL_XCVR_TX_CS_DATA_2 0x238
76 #define FSL_XCVR_TX_CS_DATA_3 0x23C
77 #define FSL_XCVR_TX_CS_DATA_4 0x240
78 #define FSL_XCVR_TX_CS_DATA_5 0x244
80 #define FSL_XCVR_TX_DPTH_CNTR_CTRL 0x260
81 #define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET 0x264
82 #define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR 0x268
83 #define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG 0x26C
85 #define FSL_XCVR_TX_DPTH_TSCR 0x270
86 #define FSL_XCVR_TX_DPTH_BCR 0x274
87 #define FSL_XCVR_TX_DPTH_BCTR 0x278
88 #define FSL_XCVR_TX_DPTH_BCRR 0x27C
90 #define FSL_XCVR_DEBUG_REG_0 0x2E0
91 #define FSL_XCVR_DEBUG_REG_1 0x2F0
112 #define FSL_XCVR_EXT_CTRL_TX_FWM_SHFT 0
113 #define FSL_XCVR_EXT_CTRL_TX_FWM_MASK GENMASK(6, 0)
125 #define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0)
140 #define FSL_XCVR_IRQ_NEW_CS BIT(0)
179 #define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0)
187 #define FSL_XCVR_RX_DPTH_CTRL_PAPB_FIFO_STATUS BIT(0)
214 #define FSL_XCVR_TX_DPTH_CTRL_CS_ACK BIT(0)
233 #define FSL_XCVR_PLL_CTRL0 0x00
234 #define FSL_XCVR_PLL_CTRL0_SET 0x04
235 #define FSL_XCVR_PLL_CTRL0_CLR 0x08
236 #define FSL_XCVR_PLL_NUM 0x20
237 #define FSL_XCVR_PLL_DEN 0x30
238 #define FSL_XCVR_PLL_PDIV 0x40
239 #define FSL_XCVR_PLL_BANDGAP_SET 0x54
240 #define FSL_XCVR_PHY_CTRL 0x00
241 #define FSL_XCVR_PHY_CTRL_SET 0x04
242 #define FSL_XCVR_PHY_CTRL_CLR 0x08
243 #define FSL_XCVR_PHY_CTRL2 0x70
244 #define FSL_XCVR_PHY_CTRL2_SET 0x74
245 #define FSL_XCVR_PHY_CTRL2_CLR 0x78
247 #define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0)
253 #define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i))
255 #define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0)
267 #define FSL_XCVR_CS_DATA_0_FS_32000 0x3000000
268 #define FSL_XCVR_CS_DATA_0_FS_44100 0x0000000
269 #define FSL_XCVR_CS_DATA_0_FS_48000 0x2000000
270 #define FSL_XCVR_CS_DATA_0_FS_64000 0xB000000
271 #define FSL_XCVR_CS_DATA_0_FS_88200 0x8000000
272 #define FSL_XCVR_CS_DATA_0_FS_96000 0xA000000
273 #define FSL_XCVR_CS_DATA_0_FS_176400 0xC000000
274 #define FSL_XCVR_CS_DATA_0_FS_192000 0xE000000
276 #define FSL_XCVR_CS_DATA_0_CH_MASK 0x3A
277 #define FSL_XCVR_CS_DATA_0_CH_U2LPCM 0x00
278 #define FSL_XCVR_CS_DATA_0_CH_UMLPCM 0x20
279 #define FSL_XCVR_CS_DATA_0_CH_U1BAUD 0x30
281 #define FSL_XCVR_CS_DATA_1_CH_MASK 0xF000
282 #define FSL_XCVR_CS_DATA_1_CH_2 0x0000
283 #define FSL_XCVR_CS_DATA_1_CH_8 0x7000
284 #define FSL_XCVR_CS_DATA_1_CH_16 0xB000
285 #define FSL_XCVR_CS_DATA_1_CH_32 0x3000
288 #define FSL_XCVR_RX_CS_CTRL_0 0x20 /* First RX CS control register */
289 #define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */
290 #define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */
291 #define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */
292 #define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */
295 #define FSL_XCVR_GP_PLL_CTRL 0x00
296 #define FSL_XCVR_GP_PLL_CTRL_SET 0x04
297 #define FSL_XCVR_GP_PLL_CTRL_CLR 0x08
298 #define FSL_XCVR_GP_PLL_CTRL_TOG 0x0C
299 #define FSL_XCVR_GP_PLL_ANA_PRG 0x10
300 #define FSL_XCVR_GP_PLL_ANA_PRG_SET 0x14
301 #define FSL_XCVR_GP_PLL_ANA_PRG_CLR 0x18
302 #define FSL_XCVR_GP_PLL_ANA_PRG_TOG 0x1C
303 #define FSL_XCVR_GP_PLL_TEST 0x20
304 #define FSL_XCVR_GP_PLL_TEST_SET 0x24
305 #define FSL_XCVR_GP_PLL_TEST_CLR 0x28
306 #define FSL_XCVR_GP_PLL_TEST_TOG 0x2C
307 #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM 0x30
308 #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_SET 0x34
309 #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_CLR 0x38
310 #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_TOG 0x3C
311 #define FSL_XCVR_GP_PLL_NUMERATOR 0x40
312 #define FSL_XCVR_GP_PLL_NUMERATOR_SET 0x44
313 #define FSL_XCVR_GP_PLL_NUMERATOR_CLR 0x48
314 #define FSL_XCVR_GP_PLL_NUMERATOR_TOG 0x4C
315 #define FSL_XCVR_GP_PLL_DENOMINATOR 0x50
316 #define FSL_XCVR_GP_PLL_DENOMINATOR_SET 0x54
317 #define FSL_XCVR_GP_PLL_DENOMINATOR_CLR 0x58
318 #define FSL_XCVR_GP_PLL_DENOMINATOR_TOG 0x5C
319 #define FSL_XCVR_GP_PLL_DIV 0x60
320 #define FSL_XCVR_GP_PLL_DIV_SET 0x64
321 #define FSL_XCVR_GP_PLL_DIV_CLR 0x68
322 #define FSL_XCVR_GP_PLL_DIV_TOG 0x6C
323 #define FSL_XCVR_GP_PLL_DFS_CTRL0 0x70
324 #define FSL_XCVR_GP_PLL_DFS_CTRL0_SET 0x74
325 #define FSL_XCVR_GP_PLL_DFS_CTRL0_CLR 0x78
326 #define FSL_XCVR_GP_PLL_DFS_CTRL0_TOG 0x7C
327 #define FSL_XCVR_GP_PLL_DFS_DIV0 0x80
328 #define FSL_XCVR_GP_PLL_DFS_DIV0_SET 0x84
329 #define FSL_XCVR_GP_PLL_DFS_DIV0_CLR 0x88
330 #define FSL_XCVR_GP_PLL_DFS_DIV0_TOG 0x8C
331 #define FSL_XCVR_GP_PLL_DFS_CTRL1 0x90
332 #define FSL_XCVR_GP_PLL_DFS_CTRL1_SET 0x94
333 #define FSL_XCVR_GP_PLL_DFS_CTRL1_CLR 0x98
334 #define FSL_XCVR_GP_PLL_DFS_CTRL1_TOG 0x9C
335 #define FSL_XCVR_GP_PLL_DFS_DIV1 0xA0
336 #define FSL_XCVR_GP_PLL_DFS_DIV1_SET 0xA4
337 #define FSL_XCVR_GP_PLL_DFS_DIV1_CLR 0xA8
338 #define FSL_XCVR_GP_PLL_DFS_DIV1_TOG 0xAC
339 #define FSL_XCVR_GP_PLL_DFS_CTRL2 0xB0
340 #define FSL_XCVR_GP_PLL_DFS_CTRL2_SET 0xB4
341 #define FSL_XCVR_GP_PLL_DFS_CTRL2_CLR 0xB8
342 #define FSL_XCVR_GP_PLL_DFS_CTRL2_TOG 0xBC
343 #define FSL_XCVR_GP_PLL_DFS_DIV2 0xC0
344 #define FSL_XCVR_GP_PLL_DFS_DIV2_SET 0xC4
345 #define FSL_XCVR_GP_PLL_DFS_DIV2_CLR 0xC8
346 #define FSL_XCVR_GP_PLL_DFS_DIV2_TOG 0xCC
347 #define FSL_XCVR_GP_PLL_DFS_CTRL3 0xD0
348 #define FSL_XCVR_GP_PLL_DFS_CTRL3_SET 0xD4
349 #define FSL_XCVR_GP_PLL_DFS_CTRL3_CLR 0xD8
350 #define FSL_XCVR_GP_PLL_DFS_CTRL3_TOG 0xDC
351 #define FSL_XCVR_GP_PLL_DFS_DIV3 0xE0
352 #define FSL_XCVR_GP_PLL_DFS_DIV3_SET 0xE4
353 #define FSL_XCVR_GP_PLL_DFS_DIV3_CLR 0xE8
354 #define FSL_XCVR_GP_PLL_DFS_DIV3_TOG 0xEC
355 #define FSL_XCVR_GP_PLL_STATUS 0xF0
356 #define FSL_XCVR_GP_PLL_STATUS_SET 0xF4
357 #define FSL_XCVR_GP_PLL_STATUS_CLR 0xF8
358 #define FSL_XCVR_GP_PLL_STATUS_TOG 0xFC
370 #define FSL_XCVR_GP_PLL_CTRL_POWERUP BIT(0)
377 #define FSL_XCVR_GP_PLL_DENOMINATOR_MFD GENMASK(29, 0)
383 #define FSL_XCVR_GP_PLL_DIV_ODIV GENMASK(7, 0)