Lines Matching +full:xcvr +full:- +full:setup
1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
71 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
108 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_arc_mode_put() local
109 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
110 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
112 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
121 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_arc_mode_get() local
123 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
143 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
144 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
153 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_capds_get() local
155 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
164 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_capds_put() local
166 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_put()
183 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_activate_ctl()
187 lockdep_assert_held(&card->snd_card->controls_rwsem); in fsl_xcvr_activate_ctl()
191 return -ENOENT; in fsl_xcvr_activate_ctl()
193 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); in fsl_xcvr_activate_ctl()
198 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
200 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
202 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); in fsl_xcvr_activate_ctl()
211 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_mode_put() local
212 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_mode_put()
213 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_mode_put()
214 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_mode_put()
217 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_mode_put()
220 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_mode_put()
222 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_mode_put()
224 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); in fsl_xcvr_mode_put()
225 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = in fsl_xcvr_mode_put()
226 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); in fsl_xcvr_mode_put()
234 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_mode_get() local
236 ucontrol->value.enumerated.item[0] = xcvr->mode; in fsl_xcvr_mode_get()
245 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
249 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) in fsl_xcvr_ai_write() argument
251 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_ai_write()
258 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); in fsl_xcvr_ai_write()
259 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); in fsl_xcvr_ai_write()
260 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); in fsl_xcvr_ai_write()
261 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); in fsl_xcvr_ai_write()
263 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, in fsl_xcvr_ai_write()
272 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) in fsl_xcvr_en_phy_pll() argument
274 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_phy_pll()
278 if (!xcvr->soc_data->use_phy) in fsl_xcvr_en_phy_pll()
289 return -EINVAL; in fsl_xcvr_en_phy_pll()
294 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_phy_pll()
301 switch (xcvr->soc_data->pll_ver) { in fsl_xcvr_en_phy_pll()
304 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET, in fsl_xcvr_en_phy_pll()
308 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0); in fsl_xcvr_en_phy_pll()
310 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0); in fsl_xcvr_en_phy_pll()
312 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0); in fsl_xcvr_en_phy_pll()
314 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
318 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR, in fsl_xcvr_en_phy_pll()
323 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
326 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
328 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ in fsl_xcvr_en_phy_pll()
330 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
333 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
337 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
340 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
346 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0); in fsl_xcvr_en_phy_pll()
348 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0); in fsl_xcvr_en_phy_pll()
349 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR, in fsl_xcvr_en_phy_pll()
352 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0); in fsl_xcvr_en_phy_pll()
355 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); in fsl_xcvr_en_phy_pll()
356 return -EINVAL; in fsl_xcvr_en_phy_pll()
359 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_phy_pll()
361 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_phy_pll()
365 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, in fsl_xcvr_en_phy_pll()
368 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_en_phy_pll()
370 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_phy_pll()
372 else /* PHY: CTRL_SET: ARC RX setup */ in fsl_xcvr_en_phy_pll()
373 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_phy_pll()
376 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); in fsl_xcvr_en_phy_pll()
385 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) in fsl_xcvr_en_aud_pll() argument
387 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_aud_pll()
390 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; in fsl_xcvr_en_aud_pll()
391 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
392 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, in fsl_xcvr_en_aud_pll()
393 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); in fsl_xcvr_en_aud_pll()
394 ret = clk_set_rate(xcvr->phy_clk, freq); in fsl_xcvr_en_aud_pll()
399 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
405 if (!xcvr->soc_data->use_phy) in fsl_xcvr_en_aud_pll()
408 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_aud_pll()
415 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_aud_pll()
417 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_aud_pll()
421 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, in fsl_xcvr_en_aud_pll()
425 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_aud_pll()
439 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_prepare() local
440 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_prepare()
442 u32 r = substream->runtime->rate, ch = substream->runtime->channels; in fsl_xcvr_prepare()
446 switch (xcvr->mode) { in fsl_xcvr_prepare()
448 if (xcvr->soc_data->spdif_only && tx) { in fsl_xcvr_prepare()
449 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
453 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); in fsl_xcvr_prepare()
460 ret = fsl_xcvr_en_aud_pll(xcvr, fout); in fsl_xcvr_prepare()
462 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", in fsl_xcvr_prepare()
467 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
470 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
475 * set SPDIF MODE - this flag is used to gate in fsl_xcvr_prepare()
485 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
491 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
495 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); in fsl_xcvr_prepare()
497 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", in fsl_xcvr_prepare()
506 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
510 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
515 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, in fsl_xcvr_prepare()
519 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
532 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); in fsl_xcvr_prepare()
534 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); in fsl_xcvr_prepare()
545 struct snd_pcm_runtime *rt = substream->runtime; in fsl_xcvr_constr()
564 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_startup() local
565 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_startup()
568 if (xcvr->streams & BIT(substream->stream)) { in fsl_xcvr_startup()
569 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); in fsl_xcvr_startup()
570 return -EBUSY; in fsl_xcvr_startup()
577 if (xcvr->soc_data->use_edma) in fsl_xcvr_startup()
578 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_xcvr_startup()
580 tx ? xcvr->dma_prms_tx.maxburst : in fsl_xcvr_startup()
581 xcvr->dma_prms_rx.maxburst); in fsl_xcvr_startup()
583 switch (xcvr->mode) { in fsl_xcvr_startup()
597 xcvr->streams |= BIT(substream->stream); in fsl_xcvr_startup()
599 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_startup()
600 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_startup()
602 /* Disable XCVR controls if there is stream started */ in fsl_xcvr_startup()
603 down_read(&card->snd_card->controls_rwsem); in fsl_xcvr_startup()
607 up_read(&card->snd_card->controls_rwsem); in fsl_xcvr_startup()
616 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_shutdown() local
617 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_shutdown()
621 xcvr->streams &= ~BIT(substream->stream); in fsl_xcvr_shutdown()
623 /* Enable XCVR controls if there is no stream started */ in fsl_xcvr_shutdown()
624 if (!xcvr->streams) { in fsl_xcvr_shutdown()
625 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_shutdown()
626 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_shutdown()
628 down_read(&card->snd_card->controls_rwsem); in fsl_xcvr_shutdown()
631 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_shutdown()
633 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_shutdown()
634 up_read(&card->snd_card->controls_rwsem); in fsl_xcvr_shutdown()
636 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_shutdown()
639 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); in fsl_xcvr_shutdown()
644 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_shutdown()
648 if (xcvr->mode == FSL_XCVR_MODE_EARC) { in fsl_xcvr_shutdown()
654 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_shutdown()
656 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); in fsl_xcvr_shutdown()
664 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_trigger() local
665 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_trigger()
673 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
677 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret); in fsl_xcvr_trigger()
682 switch (xcvr->mode) { in fsl_xcvr_trigger()
685 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
689 dev_err(dai->dev, "err updating isr %d\n", ret); in fsl_xcvr_trigger()
694 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
698 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
706 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
709 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); in fsl_xcvr_trigger()
713 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_trigger()
716 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); in fsl_xcvr_trigger()
721 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
725 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); in fsl_xcvr_trigger()
734 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
738 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); in fsl_xcvr_trigger()
742 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_trigger()
745 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret); in fsl_xcvr_trigger()
750 switch (xcvr->mode) { in fsl_xcvr_trigger()
752 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
756 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
759 if (xcvr->soc_data->spdif_only) in fsl_xcvr_trigger()
765 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
769 dev_err(dai->dev, in fsl_xcvr_trigger()
778 return -EINVAL; in fsl_xcvr_trigger()
784 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) in fsl_xcvr_load_firmware() argument
786 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_load_firmware()
791 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); in fsl_xcvr_load_firmware()
797 rem = fw->size; in fsl_xcvr_load_firmware()
803 return -ENOMEM; in fsl_xcvr_load_firmware()
807 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_load_firmware()
821 memcpy_toio(xcvr->ram_addr, fw->data + off, out); in fsl_xcvr_load_firmware()
822 rem -= out; in fsl_xcvr_load_firmware()
826 memset_io(xcvr->ram_addr + out, 0, size - out); in fsl_xcvr_load_firmware()
830 memset_io(xcvr->ram_addr, 0, size); in fsl_xcvr_load_firmware()
850 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_load_firmware()
857 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, in fsl_xcvr_load_firmware()
865 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_xcvr_type_iec958_info()
866 uinfo->count = 1; in fsl_xcvr_type_iec958_info()
874 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_iec958_bytes_info()
875 uinfo->count = sizeof_field(struct snd_aes_iec958, status); in fsl_xcvr_type_iec958_bytes_info()
884 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_rx_cs_get() local
886 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); in fsl_xcvr_rx_cs_get()
895 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_tx_cs_get() local
897 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); in fsl_xcvr_tx_cs_get()
906 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_tx_cs_put() local
908 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); in fsl_xcvr_tx_cs_put()
955 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_dai_probe() local
957 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); in fsl_xcvr_dai_probe()
959 if (xcvr->soc_data->spdif_only) in fsl_xcvr_dai_probe()
960 xcvr->mode = FSL_XCVR_MODE_SPDIF; in fsl_xcvr_dai_probe()
984 .stream_name = "CPU-Playback",
993 .stream_name = "CPU-Capture",
1004 .name = "fsl-xcvr-dai",
1060 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_readable_reg() local
1062 if (!xcvr->soc_data->use_phy) in fsl_xcvr_readable_reg()
1133 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_writeable_reg() local
1135 if (!xcvr->soc_data->use_phy) in fsl_xcvr_writeable_reg()
1203 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; in irq0_isr() local
1204 struct device *dev = &xcvr->pdev->dev; in irq0_isr()
1205 struct regmap *regmap = xcvr->regmap; in irq0_isr()
1214 if (!xcvr->soc_data->spdif_only) { in irq0_isr()
1216 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in irq0_isr()
1221 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; in irq0_isr()
1222 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; in irq0_isr()
1225 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; in irq0_isr()
1226 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; in irq0_isr()
1232 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, in irq0_isr()
1233 sizeof(xcvr->rx_iec958.status)); in irq0_isr()
1235 val = *(u32 *)(xcvr->rx_iec958.status + i*4); in irq0_isr()
1236 *(u32 *)(xcvr->rx_iec958.status + i*4) = in irq0_isr()
1278 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1296 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1297 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1298 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data},
1305 struct device *dev = &pdev->dev; in fsl_xcvr_probe()
1306 struct fsl_xcvr *xcvr; in fsl_xcvr_probe() local
1311 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); in fsl_xcvr_probe()
1312 if (!xcvr) in fsl_xcvr_probe()
1313 return -ENOMEM; in fsl_xcvr_probe()
1315 xcvr->pdev = pdev; in fsl_xcvr_probe()
1316 xcvr->soc_data = of_device_get_match_data(&pdev->dev); in fsl_xcvr_probe()
1318 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); in fsl_xcvr_probe()
1319 if (IS_ERR(xcvr->ipg_clk)) { in fsl_xcvr_probe()
1321 return PTR_ERR(xcvr->ipg_clk); in fsl_xcvr_probe()
1324 xcvr->phy_clk = devm_clk_get(dev, "phy"); in fsl_xcvr_probe()
1325 if (IS_ERR(xcvr->phy_clk)) { in fsl_xcvr_probe()
1327 return PTR_ERR(xcvr->phy_clk); in fsl_xcvr_probe()
1330 xcvr->spba_clk = devm_clk_get(dev, "spba"); in fsl_xcvr_probe()
1331 if (IS_ERR(xcvr->spba_clk)) { in fsl_xcvr_probe()
1333 return PTR_ERR(xcvr->spba_clk); in fsl_xcvr_probe()
1336 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); in fsl_xcvr_probe()
1337 if (IS_ERR(xcvr->pll_ipg_clk)) { in fsl_xcvr_probe()
1339 return PTR_ERR(xcvr->pll_ipg_clk); in fsl_xcvr_probe()
1342 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, in fsl_xcvr_probe()
1343 &xcvr->pll11k_clk); in fsl_xcvr_probe()
1345 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); in fsl_xcvr_probe()
1346 if (IS_ERR(xcvr->ram_addr)) in fsl_xcvr_probe()
1347 return PTR_ERR(xcvr->ram_addr); in fsl_xcvr_probe()
1353 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, in fsl_xcvr_probe()
1355 if (IS_ERR(xcvr->regmap)) { in fsl_xcvr_probe()
1356 dev_err(dev, "failed to init XCVR regmap: %ld\n", in fsl_xcvr_probe()
1357 PTR_ERR(xcvr->regmap)); in fsl_xcvr_probe()
1358 return PTR_ERR(xcvr->regmap); in fsl_xcvr_probe()
1361 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); in fsl_xcvr_probe()
1362 if (IS_ERR(xcvr->reset)) { in fsl_xcvr_probe()
1363 dev_err(dev, "failed to get XCVR reset control\n"); in fsl_xcvr_probe()
1364 return PTR_ERR(xcvr->reset); in fsl_xcvr_probe()
1372 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); in fsl_xcvr_probe()
1382 return -EINVAL; in fsl_xcvr_probe()
1384 xcvr->dma_prms_rx.chan_name = "rx"; in fsl_xcvr_probe()
1385 xcvr->dma_prms_tx.chan_name = "tx"; in fsl_xcvr_probe()
1386 xcvr->dma_prms_rx.addr = rx_res->start; in fsl_xcvr_probe()
1387 xcvr->dma_prms_tx.addr = tx_res->start; in fsl_xcvr_probe()
1388 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; in fsl_xcvr_probe()
1389 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; in fsl_xcvr_probe()
1391 platform_set_drvdata(pdev, xcvr); in fsl_xcvr_probe()
1393 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_probe()
1419 pm_runtime_disable(&pdev->dev); in fsl_xcvr_remove()
1424 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_runtime_suspend() local
1427 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_runtime_suspend()
1429 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_suspend()
1436 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_runtime_suspend()
1438 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_suspend()
1439 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_suspend()
1440 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_suspend()
1441 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_suspend()
1448 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_runtime_resume() local
1451 ret = reset_control_assert(xcvr->reset); in fsl_xcvr_runtime_resume()
1457 ret = clk_prepare_enable(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1463 ret = clk_prepare_enable(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1469 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1475 ret = clk_prepare_enable(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1481 regcache_cache_only(xcvr->regmap, false); in fsl_xcvr_runtime_resume()
1482 regcache_mark_dirty(xcvr->regmap); in fsl_xcvr_runtime_resume()
1483 ret = regcache_sync(xcvr->regmap); in fsl_xcvr_runtime_resume()
1490 if (xcvr->soc_data->spdif_only) in fsl_xcvr_runtime_resume()
1493 ret = reset_control_deassert(xcvr->reset); in fsl_xcvr_runtime_resume()
1499 ret = fsl_xcvr_load_firmware(xcvr); in fsl_xcvr_runtime_resume()
1506 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_resume()
1519 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1521 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1523 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1525 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1539 .name = "fsl,imx8mp-audio-xcvr",
1548 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");