soc/fsl/fsl_sai.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright 2012-2013 Freescale Semiconductor, Inc.
9 #include <linux/dma/imx-dma.h>
20 /* SAI Register Map Register */
21 #define FSL_SAI_VERID	0x00 /* SAI Version ID Register */
22 #define FSL_SAI_PARAM	0x04 /* SAI Parameter Register */
23 #define FSL_SAI_TCSR(ofs)	(0x00 + ofs) /* SAI Transmit Control */
24 #define FSL_SAI_TCR1(ofs)	(0x04 + ofs) /* SAI Transmit Configuration 1 */
25 #define FSL_SAI_TCR2(ofs)	(0x08 + ofs) /* SAI Transmit Configuration 2 */
26 #define FSL_SAI_TCR3(ofs)	(0x0c + ofs) /* SAI Transmit Configuration 3 */
27 #define FSL_SAI_TCR4(ofs)	(0x10 + ofs) /* SAI Transmit Configuration 4 */
28 #define FSL_SAI_TCR5(ofs)	(0x14 + ofs) /* SAI Transmit Configuration 5 */
29 #define FSL_SAI_TDR0	0x20 /* SAI Transmit Data 0 */
30 #define FSL_SAI_TDR1	0x24 /* SAI Transmit Data 1 */
31 #define FSL_SAI_TDR2	0x28 /* SAI Transmit Data 2 */
32 #define FSL_SAI_TDR3	0x2C /* SAI Transmit Data 3 */
33 #define FSL_SAI_TDR4	0x30 /* SAI Transmit Data 4 */
34 #define FSL_SAI_TDR5	0x34 /* SAI Transmit Data 5 */
35 #define FSL_SAI_TDR6	0x38 /* SAI Transmit Data 6 */
36 #define FSL_SAI_TDR7	0x3C /* SAI Transmit Data 7 */
37 #define FSL_SAI_TFR0	0x40 /* SAI Transmit FIFO 0 */
38 #define FSL_SAI_TFR1	0x44 /* SAI Transmit FIFO 1 */
39 #define FSL_SAI_TFR2	0x48 /* SAI Transmit FIFO 2 */
40 #define FSL_SAI_TFR3	0x4C /* SAI Transmit FIFO 3 */
41 #define FSL_SAI_TFR4	0x50 /* SAI Transmit FIFO 4 */
42 #define FSL_SAI_TFR5	0x54 /* SAI Transmit FIFO 5 */
43 #define FSL_SAI_TFR6	0x58 /* SAI Transmit FIFO 6 */
44 #define FSL_SAI_TFR7	0x5C /* SAI Transmit FIFO 7 */
45 #define FSL_SAI_TMR	0x60 /* SAI Transmit Mask */
46 #define FSL_SAI_TTCTL	0x70 /* SAI Transmit Timestamp Control Register */
47 #define FSL_SAI_TTCTN	0x74 /* SAI Transmit Timestamp Counter Register */
48 #define FSL_SAI_TBCTN	0x78 /* SAI Transmit Bit Counter Register */
49 #define FSL_SAI_TTCAP	0x7C /* SAI Transmit Timestamp Capture */
50 #define FSL_SAI_RCSR(ofs)	(0x80 + ofs) /* SAI Receive Control */
51 #define FSL_SAI_RCR1(ofs)	(0x84 + ofs)/* SAI Receive Configuration 1 */
52 #define FSL_SAI_RCR2(ofs)	(0x88 + ofs) /* SAI Receive Configuration 2 */
53 #define FSL_SAI_RCR3(ofs)	(0x8c + ofs) /* SAI Receive Configuration 3 */
54 #define FSL_SAI_RCR4(ofs)	(0x90 + ofs) /* SAI Receive Configuration 4 */
55 #define FSL_SAI_RCR5(ofs)	(0x94 + ofs) /* SAI Receive Configuration 5 */
56 #define FSL_SAI_RDR0	0xa0 /* SAI Receive Data 0 */
57 #define FSL_SAI_RDR1	0xa4 /* SAI Receive Data 1 */
58 #define FSL_SAI_RDR2	0xa8 /* SAI Receive Data 2 */
59 #define FSL_SAI_RDR3	0xac /* SAI Receive Data 3 */
60 #define FSL_SAI_RDR4	0xb0 /* SAI Receive Data 4 */
61 #define FSL_SAI_RDR5	0xb4 /* SAI Receive Data 5 */
62 #define FSL_SAI_RDR6	0xb8 /* SAI Receive Data 6 */
63 #define FSL_SAI_RDR7	0xbc /* SAI Receive Data 7 */
64 #define FSL_SAI_RFR0	0xc0 /* SAI Receive FIFO 0 */
65 #define FSL_SAI_RFR1	0xc4 /* SAI Receive FIFO 1 */
66 #define FSL_SAI_RFR2	0xc8 /* SAI Receive FIFO 2 */
67 #define FSL_SAI_RFR3	0xcc /* SAI Receive FIFO 3 */
68 #define FSL_SAI_RFR4	0xd0 /* SAI Receive FIFO 4 */
69 #define FSL_SAI_RFR5	0xd4 /* SAI Receive FIFO 5 */
70 #define FSL_SAI_RFR6	0xd8 /* SAI Receive FIFO 6 */
71 #define FSL_SAI_RFR7	0xdc /* SAI Receive FIFO 7 */
72 #define FSL_SAI_RMR	0xe0 /* SAI Receive Mask */
73 #define FSL_SAI_RTCTL	0xf0 /* SAI Receive Timestamp Control Register */
74 #define FSL_SAI_RTCTN	0xf4 /* SAI Receive Timestamp Counter Register */
75 #define FSL_SAI_RBCTN	0xf8 /* SAI Receive Bit Counter Register */
76 #define FSL_SAI_RTCAP	0xfc /* SAI Receive Timestamp Capture */
78 #define FSL_SAI_MCTL	0x100 /* SAI MCLK Control Register */
79 #define FSL_SAI_MDIV	0x104 /* SAI MCLK Divide Register */
91 /* SAI Transmit/Receive Control Register */
115 /* SAI Transmit and Receive Configuration 1 Register */
116 #define FSL_SAI_CR1_RFW_MASK(x)	((x) - 1)
118 /* SAI Transmit and Receive Configuration 2 Register */
132 /* SAI Transmit and Receive Configuration 3 Register */
138 /* SAI Transmit and Receive Configuration 4 Register */
147 #define FSL_SAI_CR4_FRSZ(x)	(((x) - 1) << 16)
149 #define FSL_SAI_CR4_SYWD(x)	(((x) - 1) << 8)
158 /* SAI Transmit and Receive Configuration 5 Register */
159 #define FSL_SAI_CR5_WNW(x)	(((x) - 1) << 24)
161 #define FSL_SAI_CR5_W0W(x)	(((x) - 1) << 16)
166 /* SAI MCLK Control Register */
177 /* SAI VERID Register */
187 /* SAI PARAM Register */
194 /* SAI MCLK Divide Register */
197 /* SAI timestamp and bitcounter */
203 /* SAI type */
211 /* SAI clock sources */
219 /* SAI data transfer numbers per DMA request */
246  * struct fsl_sai_verid - version id data
249  *           0000000000000000b - Standard feature set
250  *           0000000000000000b - Standard feature set
258  * struct fsl_sai_param - parameter data
291 	bool synchronous[2];  member
315 #define RX 0  macro