Lines Matching full:receive
50 #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
51 #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
52 #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
53 #define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
54 #define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
55 #define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
56 #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
57 #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
58 #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
59 #define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
60 #define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
61 #define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
62 #define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
63 #define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
64 #define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
65 #define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
66 #define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
67 #define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
68 #define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
69 #define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
70 #define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
71 #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
72 #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
73 #define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */
74 #define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */
75 #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
76 #define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */
91 /* SAI Transmit/Receive Control Register */
115 /* SAI Transmit and Receive Configuration 1 Register */
118 /* SAI Transmit and Receive Configuration 2 Register */
132 /* SAI Transmit and Receive Configuration 3 Register */
138 /* SAI Transmit and Receive Configuration 4 Register */
158 /* SAI Transmit and Receive Configuration 5 Register */