soc/fsl/fsl_easrc.h

1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma/imx-dma.h>
16 /* ASRC Input Write FIFO */
18 /* ASRC Output Read FIFO */
20 /* ASRC Context Control */
22 /* ASRC Context Control Extended 1 */
24 /* ASRC Context Control Extended 2 */
26 /* ASRC Control Input Access */
28 /* ASRC Datapath Processor Control Slot0 */
33 /* ASRC Datapath Processor Control Slot1 */
38 /* ASRC Context Output Control */
40 /* ASRC Control Output Access */
42 /* ASRC Sample FIFO Status */
44 /* ASRC Resampling Ratio Low */
46 /* ASRC Resampling Ratio High */
48 /* ASRC Resampling Ratio Update Control */
50 /* ASRC Resampling Ratio Update Rate */
52 /* ASRC Resampling Center Tap Coefficient Low */
54 /* ASRC Resampling Center Tap Coefficient High */
56 /* ASRC Prefilter Coefficient FIFO */
58 /* ASRC Context Resampling Coefficient Memory */
60 /* ASRC Context Resampling Coefficient Control*/
62 /* ASRC Interrupt Control */
64 /* ASRC Interrupt Status Flags */
66 /* ASRC Channel Status 0 */
68 /* ASRC Channel Status 1 */
70 /* ASRC Channel Status 2 */
72 /* ASRC Channel Status 3 */
74 /* ASRC Channel Status 4 */
76 /* ASRC Channel Status 5 */
78 /* ASRC Debug Control Register */
80 /* ASRC Debug Status Register */
86 /* ASRC Context Control (CC) */
98 #define EASRC_CC_FIFO_WTMK_MASK		((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
104 #define EASRC_CC_SAMPLE_POS_MASK	((BIT(EASRC_CC_SAMPLE_POS_WIDTH) - 1) \
113 #define EASRC_CC_BPS_MASK		((BIT(EASRC_CC_BPS_WIDTH) - 1) \
125 #define EASRC_CC_CHEN_MASK		((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
130 /* ASRC Context Control Extended 1 (CCE1) */
139 #define EASRC_CCE1_PF_EXP_MASK		((BIT(EASRC_CCE1_PF_EXP_WIDTH) - 1) \
163 #define EASRC_CCE1_RS_INIT_MASK		((BIT(EASRC_CCE1_RS_INIT_WIDTH) - 1) \
169 #define EASRC_CCE1_PF_INIT_MASK		((BIT(EASRC_CCE1_PF_INIT_WIDTH) - 1) \
174 /* ASRC Context Control Extended 2 (CCE2) */
177 #define EASRC_CCE2_ST2_TAPS_MASK	((BIT(EASRC_CCE2_ST2_TAPS_WIDTH) - 1) \
183 #define EASRC_CCE2_ST1_TAPS_MASK	((BIT(EASRC_CCE2_ST1_TAPS_WIDTH) - 1) \
188 /* ASRC Control Input Access (CIA) */
191 #define EASRC_CIA_ITER_MASK		((BIT(EASRC_CIA_ITER_WIDTH) - 1) \
197 #define EASRC_CIA_GRLEN_MASK		((BIT(EASRC_CIA_GRLEN_WIDTH) - 1) \
203 #define EASRC_CIA_ACCLEN_MASK		((BIT(EASRC_CIA_ACCLEN_WIDTH) - 1) \
208 /* ASRC Datapath Processor Control Slot0 Register0 (DPCS0R0) */
211 #define EASRC_DPCS0R0_MAXCH_MASK	((BIT(EASRC_DPCS0R0_MAXCH_WIDTH) - 1) \
217 #define EASRC_DPCS0R0_MINCH_MASK	((BIT(EASRC_DPCS0R0_MINCH_WIDTH) - 1) \
223 #define EASRC_DPCS0R0_NUMCH_MASK	((BIT(EASRC_DPCS0R0_NUMCH_WIDTH) - 1) \
229 #define EASRC_DPCS0R0_CTXNUM_MASK	((BIT(EASRC_DPCS0R0_CTXNUM_WIDTH) - 1) \
237 /* ASRC Datapath Processor Control Slot0 Register1 (DPCS0R1) */
240 #define EASRC_DPCS0R1_ST1_EXP_MASK	((BIT(EASRC_DPCS0R1_ST1_EXP_WIDTH) - 1) \
245 /* ASRC Datapath Processor Control Slot0 Register2 (DPCS0R2) */
248 #define EASRC_DPCS0R2_ST1_MA_MASK	((BIT(EASRC_DPCS0R2_ST1_MA_WIDTH) - 1) \
254 #define EASRC_DPCS0R2_ST1_SA_MASK	((BIT(EASRC_DPCS0R2_ST1_SA_WIDTH) - 1) \
259 /* ASRC Datapath Processor Control Slot0 Register3 (DPCS0R3) */
262 #define EASRC_DPCS0R3_ST2_MA_MASK	((BIT(EASRC_DPCS0R3_ST2_MA_WIDTH) - 1) \
268 #define EASRC_DPCS0R3_ST2_SA_MASK	((BIT(EASRC_DPCS0R3_ST2_SA_WIDTH) - 1) \
273 /* ASRC Context Output Control (COC) */
279 #define EASRC_COC_FIFO_WTMK_MASK	((BIT(EASRC_COC_FIFO_WTMK_WIDTH) - 1) \
285 #define EASRC_COC_SAMPLE_POS_MASK	((BIT(EASRC_COC_SAMPLE_POS_WIDTH) - 1) \
294 #define EASRC_COC_BPS_MASK		((BIT(EASRC_COC_BPS_WIDTH) - 1) \
314 /* ASRC Control Output Access (COA) */
317 #define EASRC_COA_ITER_MASK		((BIT(EASRC_COA_ITER_WIDTH) - 1) \
323 #define EASRC_COA_GRLEN_MASK		((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
329 #define EASRC_COA_ACCLEN_MASK		((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
334 /* ASRC Sample FIFO Status (SFS) */
340 #define EASRC_SFS_NSGI_MASK		((BIT(EASRC_SFS_NSGI_WIDTH) - 1) \
349 #define EASRC_SFS_NSGO_MASK		((BIT(EASRC_SFS_NSGO_WIDTH) - 1) \
354 /* ASRC Resampling Ratio Low (RRL) */
359 /* ASRC Resampling Ratio High (RRH) */
365 #define EASRC_RRH_RS_RH_MASK		((BIT(EASRC_RRH_RS_RH_WIDTH) - 1) \
370 /* ASRC Resampling Ratio Update Control (RSUC) */
375 /* ASRC Resampling Ratio Update Rate (RRUR) */
378 #define EASRC_RRUR_RRR_MASK		((BIT(EASRC_RRUR_RRR_WIDTH) - 1) \
383 /* ASRC Resampling Center Tap Coefficient Low (RCTCL) */
388 /* ASRC Resampling Center Tap Coefficient High (RCTCH) */
393 /* ASRC Prefilter Coefficient FIFO (PCF) */
398 /* ASRC Context Resampling Coefficient Memory (CRCM) */
403 /* ASRC Context Resampling Coefficient Control (CRCC) */
406 #define EASRC_CRCC_RS_CA_MASK		((BIT(EASRC_CRCC_RS_CA_WIDTH) - 1) \
412 #define EASRC_CRCC_RS_TAPS_MASK		((BIT(EASRC_CRCC_RS_TAPS_WIDTH) - 1) \
420 /* ASRC Interrupt_Control (IC) */
423 #define EASRC_IRQC_RSDM_MASK		((BIT(EASRC_IRQC_RSDM_WIDTH) - 1) \
429 #define EASRC_IRQC_OERM_MASK		((BIT(EASRC_IRQC_OERM_WIDTH) - 1) \
435 #define EASRC_IRQC_IOM_MASK		((BIT(EASRC_IRQC_IOM_WIDTH) - 1) \
440 /* ASRC Interrupt Status Flags (ISF) */
443 #define EASRC_IRQF_RSD_MASK		((BIT(EASRC_IRQF_RSD_WIDTH) - 1) \
449 #define EASRC_IRQF_OER_MASK		((BIT(EASRC_IRQF_OER_WIDTH) - 1) \
455 #define EASRC_IRQF_IFO_MASK		((BIT(EASRC_IRQF_IFO_WIDTH) - 1) \
460 /* ASRC Context Channel STAT */
465 /* ASRC Debug Control Register */
468 #define EASRC_DBGC_DMS_MASK		((BIT(EASRC_DBGC_DMS_WIDTH) - 1) \
473 /* ASRC Debug Status Register */