Lines Matching +full:4 +full:v
17 #define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
19 #define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
21 #define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
23 #define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
25 #define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
27 #define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
29 #define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
30 #define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
31 #define REG_EASRC_DPCS0R2(ctx) (0x080 + 4 * (ctx))
32 #define REG_EASRC_DPCS0R3(ctx) (0x090 + 4 * (ctx))
34 #define REG_EASRC_DPCS1R0(ctx) (0x0A0 + 4 * (ctx))
35 #define REG_EASRC_DPCS1R1(ctx) (0x0B0 + 4 * (ctx))
36 #define REG_EASRC_DPCS1R2(ctx) (0x0C0 + 4 * (ctx))
37 #define REG_EASRC_DPCS1R3(ctx) (0x0D0 + 4 * (ctx))
39 #define REG_EASRC_COC(ctx) (0x0E0 + 4 * (ctx))
41 #define REG_EASRC_COA(ctx) (0x0F0 + 4 * (ctx))
43 #define REG_EASRC_SFS(ctx) (0x100 + 4 * (ctx))
49 #define REG_EASRC_RUC(ctx) (0x130 + 4 * (ctx))
51 #define REG_EASRC_RUR(ctx) (0x140 + 4 * (ctx))
57 #define REG_EASRC_PCF(ctx) (0x160 + 4 * (ctx))
67 #define REG_EASRC_CS0(ctx) (0x180 + 4 * (ctx))
69 #define REG_EASRC_CS1(ctx) (0x190 + 4 * (ctx))
71 #define REG_EASRC_CS2(ctx) (0x1A0 + 4 * (ctx))
73 #define REG_EASRC_CS3(ctx) (0x1B0 + 4 * (ctx))
74 /* ASRC Channel Status 4 */
75 #define REG_EASRC_CS4(ctx) (0x1C0 + 4 * (ctx))
77 #define REG_EASRC_CS5(ctx) (0x1D0 + 4 * (ctx))
100 #define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \ argument
106 #define EASRC_CC_SAMPLE_POS(v) (((v) << EASRC_CC_SAMPLE_POS_SHIFT) \ argument
115 #define EASRC_CC_BPS(v) (((v) << EASRC_CC_BPS_SHIFT) \ argument
127 #define EASRC_CC_CHEN(v) (((v) << EASRC_CC_CHEN_SHIFT) \ argument
141 #define EASRC_CCE1_PF_EXP(v) (((v) << EASRC_CCE1_PF_EXP_SHIFT) \ argument
158 #define EASRC_CCE1_PF_STOP_SHIFT 4
165 #define EASRC_CCE1_RS_INIT(v) (((v) << EASRC_CCE1_RS_INIT_SHIFT) \ argument
171 #define EASRC_CCE1_PF_INIT(v) (((v) << EASRC_CCE1_PF_INIT_SHIFT) \ argument
179 #define EASRC_CCE2_ST2_TAPS(v) (((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \ argument
185 #define EASRC_CCE2_ST1_TAPS(v) (((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \ argument
193 #define EASRC_CIA_ITER(v) (((v) << EASRC_CIA_ITER_SHIFT) \ argument
199 #define EASRC_CIA_GRLEN(v) (((v) << EASRC_CIA_GRLEN_SHIFT) \ argument
205 #define EASRC_CIA_ACCLEN(v) (((v) << EASRC_CIA_ACCLEN_SHIFT) \ argument
213 #define EASRC_DPCS0R0_MAXCH(v) (((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \ argument
219 #define EASRC_DPCS0R0_MINCH(v) (((v) << EASRC_DPCS0R0_MINCH_SHIFT) \ argument
225 #define EASRC_DPCS0R0_NUMCH(v) (((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \ argument
231 #define EASRC_DPCS0R0_CTXNUM(v) (((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \ argument
242 #define EASRC_DPCS0R1_ST1_EXP(v) (((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \ argument
250 #define EASRC_DPCS0R2_ST1_MA(v) (((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \ argument
256 #define EASRC_DPCS0R2_ST1_SA(v) (((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \ argument
264 #define EASRC_DPCS0R3_ST2_MA(v) (((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \ argument
270 #define EASRC_DPCS0R3_ST2_SA(v) (((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \ argument
281 #define EASRC_COC_FIFO_WTMK(v) (((v) << EASRC_COC_FIFO_WTMK_SHIFT) \ argument
287 #define EASRC_COC_SAMPLE_POS(v) (((v) << EASRC_COC_SAMPLE_POS_SHIFT) \ argument
296 #define EASRC_COC_BPS(v) (((v) << EASRC_COC_BPS_SHIFT) \ argument
319 #define EASRC_COA_ITER(v) (((v) << EASRC_COA_ITER_SHIFT) \ argument
325 #define EASRC_COA_GRLEN(v) (((v) << EASRC_COA_GRLEN_SHIFT) \ argument
331 #define EASRC_COA_ACCLEN(v) (((v) << EASRC_COA_ACCLEN_SHIFT) \ argument
342 #define EASRC_SFS_NSGI(v) (((v) << EASRC_SFS_NSGI_SHIFT) \ argument
351 #define EASRC_SFS_NSGO(v) (((v) << EASRC_SFS_NSGO_SHIFT) \ argument
357 #define EASRC_RRL_RS_RL(v) ((v) << EASRC_RRL_RS_RL_SHIFT) argument
367 #define EASRC_RRH_RS_RH(v) (((v) << EASRC_RRH_RS_RH_SHIFT) \ argument
373 #define EASRC_RSUC_RS_RM(v) ((v) << EASRC_RSUC_RS_RM_SHIFT) argument
380 #define EASRC_RRUR_RRR(v) (((v) << EASRC_RRUR_RRR_SHIFT) \ argument
386 #define EASRC_RCTCL_RS_CL(v) ((v) << EASRC_RCTCL_RS_CL_SHIFT) argument
391 #define EASRC_RCTCH_RS_CH(v) ((v) << EASRC_RCTCH_RS_CH_SHIFT) argument
396 #define EASRC_PCF_CD(v) ((v) << EASRC_PCF_CD_SHIFT) argument
401 #define EASRC_CRCM_RS_CWD(v) ((v) << EASRC_CRCM_RS_CWD_SHIFT) argument
408 #define EASRC_CRCC_RS_CA(v) (((v) << EASRC_CRCC_RS_CA_SHIFT) \ argument
414 #define EASRC_CRCC_RS_TAPS(v) (((v) << EASRC_CRCC_RS_TAPS_SHIFT) \ argument
422 #define EASRC_IRQC_RSDM_WIDTH 4
425 #define EASRC_IRQC_RSDM(v) (((v) << EASRC_IRQC_RSDM_SHIFT) \ argument
427 #define EASRC_IRQC_OERM_SHIFT 4
428 #define EASRC_IRQC_OERM_WIDTH 4
431 #define EASRC_IRQC_OERM(v) (((v) << EASRC_IRQC_OERM_SHIFT) \ argument
434 #define EASRC_IRQC_IOM_WIDTH 4
437 #define EASRC_IRQC_IOM(v) (((v) << EASRC_IRQC_IOM_SHIFT) \ argument
442 #define EASRC_IRQF_RSD_WIDTH 4
445 #define EASRC_IRQF_RSD(v) (((v) << EASRC_IRQF_RSD_SHIFT) \ argument
447 #define EASRC_IRQF_OER_SHIFT 4
448 #define EASRC_IRQF_OER_WIDTH 4
451 #define EASRC_IRQF_OER(v) (((v) << EASRC_IRQF_OER_SHIFT) \ argument
454 #define EASRC_IRQF_IFO_WIDTH 4
457 #define EASRC_IRQF_IFO(v) (((v) << EASRC_IRQF_IFO_SHIFT) \ argument
463 #define EASRC_CSx_CSx(v) ((v) << EASRC_CSx_CSx_SHIFT) argument
470 #define EASRC_DBGC_DMS(v) (((v) << EASRC_DBGC_DMS_SHIFT) \ argument
476 #define EASRC_DBGS_DS(v) ((v) << EASRC_DBGS_DS_SHIFT) argument
479 #define EASRC_CTX_MAX_NUM 4