Lines Matching +full:1 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * wm9081.c -- WM9081 ALSA SoC Audio driver
18 #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
88 * R0 (0x00) - Software Reset
90 #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
91 #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
92 #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
95 * R2 (0x02) - Analogue Lineout
100 #define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
104 #define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
105 #define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
106 #define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
107 #define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
110 * R3 (0x03) - Analogue Speaker PGA
115 #define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
119 #define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
120 #define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
121 #define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
122 #define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
125 * R4 (0x04) - VMID Control
130 #define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
134 #define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
135 #define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
136 #define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
137 #define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
141 #define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
144 * R5 (0x05) - Bias Control 1
149 #define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
153 #define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
157 #define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
158 #define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
159 #define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
160 #define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
163 #define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
164 #define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
168 #define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
171 * R7 (0x07) - Analogue Mixer
176 #define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
180 #define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
184 #define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
187 #define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
188 #define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
192 #define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
195 * R8 (0x08) - Anti Pop Control
200 #define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
203 #define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
204 #define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
208 #define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
211 * R9 (0x09) - Analogue Speaker 1
213 #define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
214 #define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
215 #define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
216 #define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
217 #define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
218 #define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
221 * R10 (0x0A) - Analogue Speaker 2
226 #define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
230 #define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
234 #define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
237 * R11 (0x0B) - Power Management
242 #define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
246 #define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
250 #define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
254 #define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
258 #define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
261 #define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
262 #define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
266 #define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
269 * R12 (0x0C) - Clock Control 1
271 #define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
272 #define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
273 #define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
274 #define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
275 #define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
276 #define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
280 #define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
283 * R13 (0x0D) - Clock Control 2
285 #define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
286 #define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
287 #define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
288 #define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
289 #define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
290 #define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
293 * R14 (0x0E) - Clock Control 3
298 #define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
302 #define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
306 #define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
309 #define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
310 #define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
314 #define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
317 * R16 (0x10) - FLL Control 1
322 #define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
326 #define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
330 #define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
333 * R17 (0x11) - FLL Control 2
335 #define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
336 #define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
337 #define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
338 #define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
339 #define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
340 #define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
341 #define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
342 #define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
343 #define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
346 * R18 (0x12) - FLL Control 3
348 #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
349 #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
350 #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
353 * R19 (0x13) - FLL Control 4
355 #define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
356 #define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
357 #define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
358 #define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
359 #define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
360 #define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
363 * R20 (0x14) - FLL Control 5
365 #define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
366 #define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
367 #define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
368 #define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
369 #define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
370 #define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
373 * R22 (0x16) - Audio Interface 1
378 #define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
379 #define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
380 #define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
381 #define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
382 #define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
383 #define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
384 #define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
387 #define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
388 #define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
392 #define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
395 * R23 (0x17) - Audio Interface 2
400 #define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
404 #define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
408 #define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
412 #define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
416 #define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
420 #define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
421 #define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
422 #define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
423 #define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
424 #define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
425 #define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
426 #define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
429 * R24 (0x18) - Audio Interface 3
431 #define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
432 #define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
433 #define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
436 * R25 (0x19) - Audio Interface 4
438 #define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
439 #define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
440 #define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
443 * R26 (0x1A) - Interrupt Status
448 #define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
452 #define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
455 * R27 (0x1B) - Interrupt Status Mask
460 #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
464 #define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
467 * R28 (0x1C) - Interrupt Polarity
472 #define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
475 * R29 (0x1D) - Interrupt Control
479 #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
480 #define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
484 #define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
487 * R30 (0x1E) - DAC Digital 1
489 #define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
490 #define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
491 #define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
494 * R31 (0x1F) - DAC Digital 2
499 #define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
503 #define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
507 #define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
508 #define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
509 #define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
510 #define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
513 * R32 (0x20) - DRC 1
517 #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
518 #define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
519 #define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
520 #define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
521 #define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
525 #define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
529 #define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
532 #define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
533 #define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
536 * R33 (0x21) - DRC 2
538 #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
539 #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
540 #define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
541 #define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
542 #define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
543 #define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
544 #define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
545 #define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
546 #define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
547 #define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
548 #define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
549 #define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
550 #define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
551 #define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
552 #define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
553 #define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
554 #define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
555 #define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
558 * R34 (0x22) - DRC 3
560 #define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
561 #define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
562 #define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
563 #define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
564 #define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
565 #define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
568 * R35 (0x23) - DRC 4
570 #define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
571 #define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
572 #define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
573 #define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
574 #define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
575 #define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
578 * R38 (0x26) - Write Sequencer 1
582 #define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
583 #define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
587 #define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
591 #define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
592 #define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
593 #define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
594 #define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
597 * R39 (0x27) - Write Sequencer 2
599 #define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
600 #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
601 #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
605 #define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
608 * R40 (0x28) - MW Slave 1
613 #define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
617 #define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
621 #define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
624 #define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
625 #define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
628 * R42 (0x2A) - EQ 1
630 #define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
631 #define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
632 #define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
633 #define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
634 #define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
635 #define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
636 #define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
637 #define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
638 #define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
642 #define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
645 * R43 (0x2B) - EQ 2
647 #define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
648 #define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
649 #define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
650 #define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
651 #define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
652 #define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
655 * R44 (0x2C) - EQ 3
657 #define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
658 #define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
659 #define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
662 * R45 (0x2D) - EQ 4
664 #define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
665 #define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
666 #define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
669 * R46 (0x2E) - EQ 5
671 #define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
672 #define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
673 #define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
676 * R47 (0x2F) - EQ 6
678 #define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
679 #define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
680 #define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
683 * R48 (0x30) - EQ 7
685 #define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
686 #define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
687 #define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
690 * R49 (0x31) - EQ 8
692 #define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
693 #define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
694 #define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
697 * R50 (0x32) - EQ 9
699 #define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
700 #define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
701 #define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
704 * R51 (0x33) - EQ 10
706 #define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
707 #define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
708 #define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
711 * R52 (0x34) - EQ 11
713 #define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
714 #define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
715 #define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
718 * R53 (0x35) - EQ 12
720 #define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
721 #define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
722 #define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
725 * R54 (0x36) - EQ 13
727 #define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
728 #define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
729 #define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
732 * R55 (0x37) - EQ 14
734 #define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
735 #define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
736 #define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
739 * R56 (0x38) - EQ 15
741 #define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
742 #define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
743 #define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
746 * R57 (0x39) - EQ 16
748 #define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
749 #define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
750 #define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
753 * R58 (0x3A) - EQ 17
755 #define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
756 #define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
757 #define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
760 * R59 (0x3B) - EQ 18
762 #define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
763 #define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
764 #define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
767 * R60 (0x3C) - EQ 19
769 #define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
770 #define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
771 #define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
774 * R61 (0x3D) - EQ 20
776 #define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
777 #define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
778 #define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */