Lines Matching +full:1 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm8995.h -- WM8995 ALSA SoC Audio driver
753 * R0 (0x00) - Software Reset
755 #define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
756 #define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
757 #define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
760 * R1 (0x01) - Power Management (1)
765 #define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
769 #define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
773 #define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */
777 #define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */
781 #define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
785 #define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
789 #define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */
792 * R2 (0x02) - Power Management (2)
797 #define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
801 #define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
805 #define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
808 #define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
809 #define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
812 * R3 (0x03) - Power Management (3)
817 #define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
821 #define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
825 #define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
829 #define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
833 #define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
837 #define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
841 #define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */
845 #define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */
849 #define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
853 #define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
857 #define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
861 #define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
864 #define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
865 #define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
869 #define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
872 * R4 (0x04) - Power Management (4)
877 #define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
881 #define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
885 #define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
889 #define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
893 #define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
897 #define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
901 #define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
905 #define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
908 #define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
909 #define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
913 #define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
916 * R5 (0x05) - Power Management (5)
918 #define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */
919 #define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */
920 #define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */
921 #define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */
922 #define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */
923 #define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */
927 #define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
928 #define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
929 #define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
930 #define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
934 #define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
937 #define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
938 #define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
942 #define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
945 * R16 (0x10) - Left Line Input 1 Volume
950 #define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
954 #define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
955 #define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
956 #define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
957 #define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
960 * R17 (0x11) - Right Line Input 1 Volume
965 #define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
969 #define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
970 #define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
971 #define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
972 #define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
975 * R18 (0x12) - Left Line Input Control
977 #define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */
978 #define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */
979 #define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */
980 #define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */
981 #define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */
982 #define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */
983 #define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */
984 #define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */
985 #define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */
988 * R24 (0x18) - DAC1 Left Volume
993 #define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
997 #define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
998 #define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
999 #define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1000 #define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
1003 * R25 (0x19) - DAC1 Right Volume
1008 #define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
1012 #define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1013 #define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
1014 #define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
1015 #define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
1018 * R26 (0x1A) - DAC2 Left Volume
1023 #define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
1027 #define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1028 #define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
1029 #define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
1030 #define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
1033 * R27 (0x1B) - DAC2 Right Volume
1038 #define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
1042 #define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1043 #define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
1044 #define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
1045 #define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
1048 * R28 (0x1C) - Output Volume ZC (1)
1053 #define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */
1057 #define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */
1060 #define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */
1061 #define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1065 #define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1068 * R32 (0x20) - MICBIAS (1)
1073 #define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1074 #define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */
1075 #define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */
1076 #define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */
1080 #define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1083 * R33 (0x21) - MICBIAS (2)
1088 #define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1089 #define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */
1090 #define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */
1091 #define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */
1095 #define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1098 * R40 (0x28) - LDO 1
1103 #define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */
1104 #define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */
1105 #define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */
1106 #define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */
1110 #define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1113 * R41 (0x29) - LDO 2
1118 #define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */
1119 #define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */
1120 #define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */
1121 #define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */
1125 #define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1128 * R48 (0x30) - Accessory Detect Mode1
1130 #define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */
1131 #define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */
1132 #define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */
1135 * R49 (0x31) - Accessory Detect Mode2
1140 #define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */
1143 * R52 (0x34) - Headphone Detect1
1147 #define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */
1148 #define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */
1152 #define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */
1155 * R53 (0x35) - Headphone Detect2
1160 #define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */
1161 #define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1162 #define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1163 #define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1166 * R56 (0x38) - Mic Detect (1)
1168 #define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */
1169 #define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */
1170 #define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */
1171 #define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */
1172 #define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */
1173 #define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */
1176 #define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1177 #define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1181 #define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */
1184 * R57 (0x39) - Mic Detect (2)
1186 #define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */
1187 #define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */
1188 #define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */
1191 #define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */
1192 #define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */
1196 #define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */
1199 * R64 (0x40) - Charge Pump (1)
1203 #define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */
1204 #define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */
1207 * R69 (0x45) - Class W (1)
1209 #define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
1210 #define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
1211 #define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
1215 #define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
1218 * R80 (0x50) - DC Servo (1)
1223 #define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
1227 #define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
1230 #define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
1231 #define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
1235 #define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
1238 * R81 (0x51) - DC Servo (2)
1242 #define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
1243 #define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
1247 #define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
1251 #define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
1255 #define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
1259 #define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
1263 #define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
1267 #define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
1271 #define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
1275 #define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
1279 #define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
1283 #define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
1287 #define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
1291 #define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
1295 #define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
1298 #define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
1299 #define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
1303 #define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
1306 * R82 (0x52) - DC Servo (3)
1308 #define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
1309 #define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
1310 #define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
1311 #define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
1312 #define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
1313 #define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
1316 * R84 (0x54) - DC Servo (5)
1318 #define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */
1319 #define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */
1320 #define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */
1321 #define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
1322 #define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
1323 #define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
1326 * R85 (0x55) - DC Servo (6)
1328 #define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */
1329 #define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1330 #define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1331 #define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
1332 #define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
1333 #define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
1336 * R86 (0x56) - DC Servo (7)
1338 #define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
1339 #define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1340 #define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1341 #define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
1342 #define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
1343 #define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
1346 * R87 (0x57) - DC Servo Readback 0
1348 #define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
1349 #define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
1350 #define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
1351 #define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
1352 #define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1353 #define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1354 #define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
1355 #define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
1356 #define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
1359 * R96 (0x60) - Analogue HP (1)
1364 #define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
1368 #define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
1372 #define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
1376 #define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
1380 #define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
1383 #define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
1384 #define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1387 * R97 (0x61) - Analogue HP (2)
1392 #define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */
1396 #define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */
1400 #define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */
1404 #define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */
1408 #define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */
1411 #define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */
1412 #define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */
1415 * R256 (0x100) - Chip Revision
1417 #define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
1418 #define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
1419 #define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
1422 * R257 (0x101) - Control Interface (1)
1426 #define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */
1427 #define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */
1431 #define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
1435 #define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
1439 #define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */
1443 #define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */
1446 * R258 (0x102) - Control Interface (2)
1451 #define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */
1454 * R272 (0x110) - Write Sequencer Ctrl (1)
1458 #define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
1459 #define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1463 #define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1467 #define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */
1468 #define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
1469 #define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
1470 #define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
1473 * R273 (0x111) - Write Sequencer Ctrl (2)
1478 #define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1479 #define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
1480 #define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
1481 #define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
1484 * R512 (0x200) - AIF1 Clocking (1)
1486 #define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
1487 #define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
1488 #define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
1492 #define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
1495 #define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
1496 #define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
1500 #define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
1503 * R513 (0x201) - AIF1 Clocking (2)
1505 #define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
1506 #define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
1507 #define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
1508 #define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
1509 #define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
1510 #define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
1513 * R516 (0x204) - AIF2 Clocking (1)
1515 #define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
1516 #define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
1517 #define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
1521 #define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
1524 #define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
1525 #define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
1529 #define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
1532 * R517 (0x205) - AIF2 Clocking (2)
1534 #define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
1535 #define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
1536 #define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
1537 #define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
1538 #define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
1539 #define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
1542 * R520 (0x208) - Clocking (1)
1547 #define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */
1551 #define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1555 #define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */
1559 #define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */
1562 #define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
1563 #define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
1567 #define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
1570 * R521 (0x209) - Clocking (2)
1572 #define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
1573 #define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
1574 #define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
1575 #define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */
1576 #define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */
1577 #define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */
1578 #define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
1579 #define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
1580 #define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
1583 * R528 (0x210) - AIF1 Rate
1585 #define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
1586 #define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
1587 #define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
1588 #define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
1589 #define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
1590 #define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
1593 * R529 (0x211) - AIF2 Rate
1595 #define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
1596 #define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
1597 #define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
1598 #define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
1599 #define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
1600 #define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
1603 * R530 (0x212) - Rate Status
1605 #define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
1606 #define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
1607 #define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
1610 * R544 (0x220) - FLL1 Control (1)
1614 #define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
1615 #define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
1619 #define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1622 * R545 (0x221) - FLL1 Control (2)
1624 #define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
1625 #define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
1626 #define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
1627 #define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
1628 #define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
1629 #define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
1630 #define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
1631 #define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
1632 #define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
1635 * R546 (0x222) - FLL1 Control (3)
1637 #define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
1638 #define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
1639 #define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
1642 * R547 (0x223) - FLL1 Control (4)
1644 #define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
1645 #define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
1646 #define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
1647 #define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */
1648 #define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */
1649 #define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */
1652 * R548 (0x224) - FLL1 Control (5)
1654 #define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
1655 #define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
1656 #define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
1660 #define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
1661 #define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */
1662 #define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */
1663 #define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */
1664 #define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */
1665 #define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
1666 #define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
1669 * R576 (0x240) - FLL2 Control (1)
1673 #define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
1674 #define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
1678 #define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1681 * R577 (0x241) - FLL2 Control (2)
1683 #define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
1684 #define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
1685 #define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
1686 #define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
1687 #define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
1688 #define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
1689 #define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
1690 #define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
1691 #define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
1694 * R578 (0x242) - FLL2 Control (3)
1696 #define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
1697 #define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
1698 #define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
1701 * R579 (0x243) - FLL2 Control (4)
1703 #define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
1704 #define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
1705 #define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
1706 #define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */
1707 #define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */
1708 #define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */
1711 * R580 (0x244) - FLL2 Control (5)
1713 #define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
1714 #define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
1715 #define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
1719 #define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
1720 #define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */
1721 #define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */
1722 #define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */
1723 #define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */
1724 #define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
1725 #define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
1728 * R768 (0x300) - AIF1 Control (1)
1732 #define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
1733 #define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
1737 #define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
1741 #define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
1745 #define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1749 #define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
1750 #define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
1751 #define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
1752 #define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
1753 #define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
1754 #define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
1755 #define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
1758 * R769 (0x301) - AIF1 Control (2)
1762 #define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
1763 #define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
1767 #define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
1768 #define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
1769 #define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
1770 #define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
1774 #define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
1778 #define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
1782 #define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
1785 #define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
1786 #define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
1790 #define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
1793 * R770 (0x302) - AIF1 Master/Slave
1797 #define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
1798 #define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1802 #define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
1806 #define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
1810 #define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
1813 * R771 (0x303) - AIF1 BCLK
1815 #define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */
1816 #define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */
1817 #define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */
1820 * R772 (0x304) - AIF1ADC LRCLK
1825 #define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
1826 #define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
1827 #define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
1828 #define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
1831 * R773 (0x305) - AIF1DAC LRCLK
1836 #define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
1837 #define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
1838 #define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
1839 #define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
1842 * R774 (0x306) - AIF1DAC Data
1846 #define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
1847 #define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
1851 #define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
1854 * R775 (0x307) - AIF1ADC Data
1858 #define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
1859 #define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
1863 #define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
1866 * R784 (0x310) - AIF2 Control (1)
1870 #define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
1871 #define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
1875 #define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
1879 #define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
1883 #define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
1887 #define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
1891 #define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
1892 #define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
1893 #define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
1894 #define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
1895 #define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
1896 #define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
1897 #define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
1900 * R785 (0x311) - AIF2 Control (2)
1904 #define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
1905 #define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
1909 #define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
1913 #define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
1917 #define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
1918 #define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
1919 #define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
1920 #define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
1924 #define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
1928 #define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
1932 #define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
1935 #define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
1936 #define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
1940 #define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
1943 * R786 (0x312) - AIF2 Master/Slave
1947 #define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
1948 #define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
1952 #define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
1956 #define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
1960 #define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
1963 * R787 (0x313) - AIF2 BCLK
1965 #define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */
1966 #define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */
1967 #define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */
1970 * R788 (0x314) - AIF2ADC LRCLK
1975 #define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
1976 #define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
1977 #define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
1978 #define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
1981 * R789 (0x315) - AIF2DAC LRCLK
1986 #define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
1987 #define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
1988 #define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
1989 #define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
1992 * R790 (0x316) - AIF2DAC Data
1996 #define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
1997 #define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
2001 #define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
2004 * R791 (0x317) - AIF2ADC Data
2008 #define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
2009 #define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
2013 #define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
2016 * R1024 (0x400) - AIF1 ADC1 Left Volume
2021 #define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2022 #define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
2023 #define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
2024 #define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
2027 * R1025 (0x401) - AIF1 ADC1 Right Volume
2032 #define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2033 #define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
2034 #define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
2035 #define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
2038 * R1026 (0x402) - AIF1 DAC1 Left Volume
2043 #define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2044 #define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
2045 #define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
2046 #define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
2049 * R1027 (0x403) - AIF1 DAC1 Right Volume
2054 #define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2055 #define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
2056 #define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
2057 #define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
2060 * R1028 (0x404) - AIF1 ADC2 Left Volume
2065 #define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2066 #define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
2067 #define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
2068 #define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
2071 * R1029 (0x405) - AIF1 ADC2 Right Volume
2076 #define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2077 #define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
2078 #define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
2079 #define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
2082 * R1030 (0x406) - AIF1 DAC2 Left Volume
2087 #define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2088 #define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
2089 #define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
2090 #define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
2093 * R1031 (0x407) - AIF1 DAC2 Right Volume
2098 #define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2099 #define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
2100 #define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
2101 #define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
2104 * R1040 (0x410) - AIF1 ADC1 Filters
2108 #define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */
2109 #define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */
2113 #define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
2117 #define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
2121 #define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */
2122 #define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */
2123 #define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */
2124 #define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */
2127 * R1041 (0x411) - AIF1 ADC2 Filters
2132 #define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
2136 #define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
2140 #define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */
2141 #define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */
2142 #define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */
2143 #define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */
2146 * R1056 (0x420) - AIF1 DAC1 Filters (1)
2151 #define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
2155 #define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
2159 #define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
2163 #define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
2164 #define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
2165 #define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
2166 #define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
2169 * R1057 (0x421) - AIF1 DAC1 Filters (2)
2171 #define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
2172 #define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
2173 #define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
2177 #define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
2180 * R1058 (0x422) - AIF1 DAC2 Filters (1)
2185 #define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
2189 #define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
2193 #define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
2197 #define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
2198 #define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
2199 #define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
2200 #define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
2203 * R1059 (0x423) - AIF1 DAC2 Filters (2)
2205 #define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
2206 #define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
2207 #define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
2211 #define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
2214 * R1088 (0x440) - AIF1 DRC1 (1)
2216 #define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2217 #define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2218 #define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2219 #define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2220 #define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2221 #define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2225 #define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
2229 #define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
2233 #define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
2237 #define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
2241 #define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
2245 #define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
2249 #define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
2252 #define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
2253 #define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
2257 #define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
2260 * R1089 (0x441) - AIF1 DRC1 (2)
2262 #define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
2263 #define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
2264 #define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
2265 #define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
2266 #define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
2267 #define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
2268 #define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
2269 #define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
2270 #define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
2271 #define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
2272 #define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
2273 #define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
2276 * R1090 (0x442) - AIF1 DRC1 (3)
2278 #define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2279 #define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2280 #define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2281 #define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
2282 #define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
2283 #define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
2284 #define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
2285 #define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
2286 #define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
2287 #define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
2288 #define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
2289 #define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
2290 #define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
2291 #define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
2292 #define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
2293 #define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
2294 #define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
2295 #define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
2298 * R1091 (0x443) - AIF1 DRC1 (4)
2300 #define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
2301 #define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
2302 #define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
2303 #define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
2304 #define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
2305 #define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
2308 * R1092 (0x444) - AIF1 DRC1 (5)
2310 #define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
2311 #define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2312 #define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2313 #define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
2314 #define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
2315 #define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
2318 * R1104 (0x450) - AIF1 DRC2 (1)
2320 #define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2321 #define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2322 #define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2323 #define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2324 #define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2325 #define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2329 #define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
2333 #define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
2337 #define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
2341 #define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
2345 #define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
2349 #define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
2353 #define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
2356 #define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
2357 #define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
2361 #define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
2364 * R1105 (0x451) - AIF1 DRC2 (2)
2366 #define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
2367 #define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
2368 #define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
2369 #define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
2370 #define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
2371 #define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
2372 #define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
2373 #define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
2374 #define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
2375 #define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
2376 #define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
2377 #define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
2380 * R1106 (0x452) - AIF1 DRC2 (3)
2382 #define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2383 #define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2384 #define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2385 #define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
2386 #define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
2387 #define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
2388 #define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
2389 #define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
2390 #define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
2391 #define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
2392 #define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
2393 #define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
2394 #define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
2395 #define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
2396 #define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
2397 #define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
2398 #define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
2399 #define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
2402 * R1107 (0x453) - AIF1 DRC2 (4)
2404 #define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
2405 #define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
2406 #define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
2407 #define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
2408 #define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
2409 #define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
2412 * R1108 (0x454) - AIF1 DRC2 (5)
2414 #define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
2415 #define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2416 #define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2417 #define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
2418 #define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
2419 #define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
2422 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
2424 #define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2425 #define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2426 #define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2427 #define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2428 #define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2429 #define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2430 #define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2431 #define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2432 #define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2436 #define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
2439 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
2441 #define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2442 #define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2443 #define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2444 #define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2445 #define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2446 #define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2449 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
2451 #define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
2452 #define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
2453 #define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
2456 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
2458 #define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
2459 #define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
2460 #define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
2463 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
2465 #define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
2466 #define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2467 #define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2470 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
2472 #define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
2473 #define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
2474 #define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
2477 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
2479 #define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
2480 #define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
2481 #define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
2484 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
2486 #define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
2487 #define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
2488 #define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
2491 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
2493 #define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
2494 #define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2495 #define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2498 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
2500 #define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
2501 #define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
2502 #define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
2505 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
2507 #define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
2508 #define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
2509 #define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
2512 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
2514 #define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
2515 #define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
2516 #define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
2519 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
2521 #define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
2522 #define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2523 #define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2526 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
2528 #define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
2529 #define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
2530 #define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
2533 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
2535 #define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
2536 #define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
2537 #define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
2540 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
2542 #define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
2543 #define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
2544 #define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
2547 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
2549 #define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
2550 #define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2551 #define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2554 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
2556 #define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
2557 #define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
2558 #define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
2561 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
2563 #define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
2564 #define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
2565 #define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
2568 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
2570 #define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
2571 #define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2572 #define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2575 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
2577 #define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2578 #define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2579 #define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2580 #define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2581 #define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2582 #define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2583 #define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2584 #define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2585 #define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2589 #define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
2592 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
2594 #define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2595 #define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2596 #define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2597 #define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2598 #define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2599 #define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2602 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
2604 #define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
2605 #define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
2606 #define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
2609 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
2611 #define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
2612 #define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
2613 #define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
2616 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
2618 #define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
2619 #define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2620 #define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2623 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
2625 #define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
2626 #define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
2627 #define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
2630 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
2632 #define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
2633 #define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
2634 #define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
2637 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
2639 #define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
2640 #define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
2641 #define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
2644 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
2646 #define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
2647 #define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2648 #define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2651 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
2653 #define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
2654 #define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
2655 #define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
2658 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
2660 #define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
2661 #define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
2662 #define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
2665 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
2667 #define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
2668 #define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
2669 #define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
2672 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
2674 #define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
2675 #define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2676 #define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2679 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
2681 #define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
2682 #define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
2683 #define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
2686 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
2688 #define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
2689 #define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
2690 #define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
2693 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
2695 #define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
2696 #define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
2697 #define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
2700 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
2702 #define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
2703 #define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2704 #define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2707 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
2709 #define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
2710 #define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
2711 #define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
2714 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
2716 #define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
2717 #define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
2718 #define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
2721 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
2723 #define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
2724 #define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2725 #define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2728 * R1280 (0x500) - AIF2 ADC Left Volume
2733 #define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2734 #define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
2735 #define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
2736 #define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
2739 * R1281 (0x501) - AIF2 ADC Right Volume
2744 #define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2745 #define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
2746 #define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
2747 #define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
2750 * R1282 (0x502) - AIF2 DAC Left Volume
2755 #define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2756 #define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
2757 #define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
2758 #define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
2761 * R1283 (0x503) - AIF2 DAC Right Volume
2766 #define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2767 #define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
2768 #define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
2769 #define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
2772 * R1296 (0x510) - AIF2 ADC Filters
2776 #define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
2777 #define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
2781 #define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
2785 #define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
2789 #define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */
2790 #define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */
2791 #define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */
2792 #define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */
2795 * R1312 (0x520) - AIF2 DAC Filters (1)
2800 #define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
2804 #define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
2808 #define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
2812 #define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
2813 #define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
2814 #define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
2815 #define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
2818 * R1313 (0x521) - AIF2 DAC Filters (2)
2820 #define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
2821 #define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
2822 #define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
2826 #define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
2829 * R1344 (0x540) - AIF2 DRC (1)
2831 #define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2832 #define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2833 #define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2834 #define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
2835 #define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
2836 #define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
2840 #define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
2844 #define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
2848 #define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
2852 #define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
2856 #define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
2860 #define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
2864 #define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
2867 #define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
2868 #define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
2872 #define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
2875 * R1345 (0x541) - AIF2 DRC (2)
2877 #define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
2878 #define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
2879 #define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
2880 #define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
2881 #define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
2882 #define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
2883 #define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
2884 #define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
2885 #define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
2886 #define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
2887 #define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
2888 #define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
2891 * R1346 (0x542) - AIF2 DRC (3)
2893 #define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
2894 #define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
2895 #define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
2896 #define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
2897 #define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
2898 #define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
2899 #define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
2900 #define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
2901 #define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
2902 #define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
2903 #define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
2904 #define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
2905 #define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
2906 #define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
2907 #define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
2908 #define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
2909 #define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
2910 #define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
2913 * R1347 (0x543) - AIF2 DRC (4)
2915 #define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
2916 #define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
2917 #define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
2918 #define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
2919 #define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
2920 #define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
2923 * R1348 (0x544) - AIF2 DRC (5)
2925 #define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
2926 #define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2927 #define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2928 #define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
2929 #define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
2930 #define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
2933 * R1408 (0x580) - AIF2 EQ Gains (1)
2935 #define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2936 #define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2937 #define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2938 #define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2939 #define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2940 #define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2941 #define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2942 #define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2943 #define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2947 #define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
2950 * R1409 (0x581) - AIF2 EQ Gains (2)
2952 #define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2953 #define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2954 #define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2955 #define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2956 #define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2957 #define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2960 * R1410 (0x582) - AIF2 EQ Band 1 A
2962 #define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
2963 #define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
2964 #define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
2967 * R1411 (0x583) - AIF2 EQ Band 1 B
2969 #define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
2970 #define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
2971 #define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
2974 * R1412 (0x584) - AIF2 EQ Band 1 PG
2976 #define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
2977 #define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
2978 #define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
2981 * R1413 (0x585) - AIF2 EQ Band 2 A
2983 #define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
2984 #define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
2985 #define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
2988 * R1414 (0x586) - AIF2 EQ Band 2 B
2990 #define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
2991 #define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
2992 #define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
2995 * R1415 (0x587) - AIF2 EQ Band 2 C
2997 #define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
2998 #define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
2999 #define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
3002 * R1416 (0x588) - AIF2 EQ Band 2 PG
3004 #define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
3005 #define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
3006 #define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
3009 * R1417 (0x589) - AIF2 EQ Band 3 A
3011 #define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
3012 #define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
3013 #define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
3016 * R1418 (0x58A) - AIF2 EQ Band 3 B
3018 #define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
3019 #define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
3020 #define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
3023 * R1419 (0x58B) - AIF2 EQ Band 3 C
3025 #define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
3026 #define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
3027 #define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
3030 * R1420 (0x58C) - AIF2 EQ Band 3 PG
3032 #define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
3033 #define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
3034 #define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
3037 * R1421 (0x58D) - AIF2 EQ Band 4 A
3039 #define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
3040 #define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
3041 #define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
3044 * R1422 (0x58E) - AIF2 EQ Band 4 B
3046 #define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
3047 #define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
3048 #define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
3051 * R1423 (0x58F) - AIF2 EQ Band 4 C
3053 #define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
3054 #define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
3055 #define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
3058 * R1424 (0x590) - AIF2 EQ Band 4 PG
3060 #define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
3061 #define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
3062 #define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
3065 * R1425 (0x591) - AIF2 EQ Band 5 A
3067 #define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
3068 #define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
3069 #define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
3072 * R1426 (0x592) - AIF2 EQ Band 5 B
3074 #define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
3075 #define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
3076 #define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
3079 * R1427 (0x593) - AIF2 EQ Band 5 PG
3081 #define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
3082 #define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
3083 #define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
3086 * R1536 (0x600) - DAC1 Mixer Volumes
3088 #define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */
3089 #define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */
3090 #define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */
3091 #define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */
3092 #define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */
3093 #define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */
3096 * R1537 (0x601) - DAC1 Left Mixer Routing
3101 #define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3105 #define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3109 #define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
3112 #define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
3113 #define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
3117 #define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
3120 * R1538 (0x602) - DAC1 Right Mixer Routing
3125 #define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3129 #define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3133 #define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
3136 #define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
3137 #define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
3141 #define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
3144 * R1539 (0x603) - DAC2 Mixer Volumes
3146 #define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */
3147 #define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */
3148 #define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */
3149 #define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */
3150 #define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */
3151 #define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */
3154 * R1540 (0x604) - DAC2 Left Mixer Routing
3159 #define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3163 #define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
3167 #define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
3170 #define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
3171 #define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
3175 #define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
3178 * R1541 (0x605) - DAC2 Right Mixer Routing
3183 #define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
3187 #define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
3191 #define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
3194 #define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
3195 #define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
3199 #define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
3202 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
3206 #define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
3207 #define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
3211 #define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
3214 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
3218 #define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
3219 #define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
3223 #define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
3226 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
3230 #define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
3231 #define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
3235 #define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
3238 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
3242 #define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
3243 #define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
3247 #define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
3250 * R1552 (0x610) - DAC Softmute
3254 #define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
3255 #define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
3259 #define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
3262 * R1568 (0x620) - Oversampling
3266 #define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
3267 #define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
3271 #define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
3274 * R1569 (0x621) - Sidetone
3279 #define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */
3280 #define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
3281 #define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
3282 #define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
3286 #define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */
3289 #define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */
3290 #define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */
3294 #define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */
3297 * R1792 (0x700) - GPIO 1
3301 #define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */
3302 #define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */
3306 #define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */
3310 #define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */
3314 #define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */
3318 #define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
3322 #define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */
3326 #define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */
3327 #define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */
3328 #define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */
3329 #define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */
3332 * R1793 (0x701) - GPIO 2
3336 #define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */
3337 #define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */
3341 #define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */
3345 #define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */
3349 #define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */
3353 #define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
3357 #define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */
3361 #define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */
3362 #define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */
3363 #define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */
3364 #define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */
3367 * R1794 (0x702) - GPIO 3
3371 #define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */
3372 #define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */
3376 #define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */
3380 #define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */
3384 #define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */
3388 #define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
3392 #define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */
3396 #define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */
3397 #define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */
3398 #define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */
3399 #define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */
3402 * R1795 (0x703) - GPIO 4
3406 #define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */
3407 #define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */
3411 #define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */
3415 #define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */
3419 #define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */
3423 #define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3427 #define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */
3431 #define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */
3432 #define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */
3433 #define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */
3434 #define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */
3437 * R1796 (0x704) - GPIO 5
3441 #define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */
3442 #define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */
3446 #define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */
3450 #define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */
3454 #define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */
3458 #define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3462 #define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */
3466 #define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */
3467 #define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */
3468 #define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */
3469 #define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */
3472 * R1797 (0x705) - GPIO 6
3476 #define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */
3477 #define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */
3481 #define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */
3485 #define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */
3489 #define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */
3493 #define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
3497 #define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */
3501 #define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */
3502 #define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */
3503 #define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */
3504 #define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */
3507 * R1798 (0x706) - GPIO 7
3511 #define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */
3512 #define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */
3516 #define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */
3520 #define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */
3524 #define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */
3528 #define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */
3532 #define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */
3536 #define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */
3537 #define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */
3538 #define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */
3539 #define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */
3542 * R1799 (0x707) - GPIO 8
3546 #define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */
3547 #define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */
3551 #define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */
3555 #define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */
3559 #define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */
3563 #define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */
3567 #define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */
3571 #define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */
3572 #define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */
3573 #define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */
3574 #define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */
3577 * R1800 (0x708) - GPIO 9
3581 #define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */
3582 #define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */
3586 #define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */
3590 #define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */
3594 #define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */
3598 #define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */
3602 #define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */
3606 #define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */
3607 #define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */
3608 #define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */
3609 #define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */
3612 * R1801 (0x709) - GPIO 10
3616 #define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */
3617 #define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */
3621 #define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */
3625 #define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */
3629 #define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */
3633 #define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */
3637 #define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */
3641 #define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */
3642 #define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */
3643 #define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */
3644 #define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */
3647 * R1802 (0x70A) - GPIO 11
3651 #define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */
3652 #define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */
3656 #define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */
3660 #define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */
3664 #define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */
3668 #define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */
3672 #define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */
3676 #define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */
3677 #define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */
3678 #define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */
3679 #define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */
3682 * R1803 (0x70B) - GPIO 12
3686 #define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */
3687 #define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */
3691 #define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */
3695 #define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */
3699 #define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */
3703 #define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */
3707 #define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */
3711 #define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */
3712 #define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */
3713 #define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */
3714 #define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */
3717 * R1804 (0x70C) - GPIO 13
3721 #define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */
3722 #define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */
3726 #define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */
3730 #define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */
3734 #define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */
3738 #define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */
3742 #define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */
3746 #define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */
3747 #define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */
3748 #define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */
3749 #define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */
3752 * R1805 (0x70D) - GPIO 14
3756 #define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */
3757 #define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */
3761 #define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */
3765 #define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */
3769 #define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */
3773 #define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */
3777 #define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */
3781 #define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */
3782 #define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */
3783 #define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */
3784 #define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */
3787 * R1824 (0x720) - Pull Control (1)
3792 #define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
3796 #define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3800 #define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3804 #define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */
3808 #define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3812 #define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
3816 #define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3820 #define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
3824 #define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
3828 #define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
3832 #define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
3835 #define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
3836 #define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
3840 #define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
3843 * R1825 (0x721) - Pull Control (2)
3848 #define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3852 #define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */
3856 #define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */
3859 * R1840 (0x730) - Interrupt Status 1
3864 #define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */
3868 #define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */
3872 #define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */
3876 #define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */
3880 #define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */
3884 #define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */
3888 #define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */
3892 #define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */
3896 #define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */
3900 #define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */
3904 #define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */
3908 #define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */
3911 #define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */
3912 #define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */
3916 #define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */
3919 * R1841 (0x731) - Interrupt Status 2
3924 #define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */
3928 #define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */
3932 #define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3936 #define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3940 #define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */
3944 #define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */
3948 #define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */
3952 #define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
3956 #define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
3960 #define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
3964 #define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
3967 #define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */
3968 #define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */
3972 #define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */
3975 * R1842 (0x732) - Interrupt Raw Status 2
3980 #define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */
3984 #define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */
3988 #define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
3992 #define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
3996 #define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */
4000 #define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */
4004 #define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */
4008 #define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */
4012 #define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */
4016 #define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
4020 #define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
4023 * R1848 (0x738) - Interrupt Status 1 Mask
4028 #define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
4032 #define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
4036 #define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
4040 #define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
4044 #define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
4048 #define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
4052 #define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
4056 #define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
4060 #define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
4064 #define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
4068 #define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
4072 #define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
4075 #define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
4076 #define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
4080 #define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
4083 * R1849 (0x739) - Interrupt Status 2 Mask
4088 #define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */
4092 #define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */
4096 #define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
4100 #define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
4104 #define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */
4108 #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */
4112 #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */
4116 #define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
4120 #define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
4124 #define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
4128 #define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
4131 #define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */
4132 #define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */
4136 #define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
4139 * R1856 (0x740) - Interrupt Control
4144 #define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */
4147 * R2048 (0x800) - Left PDM Speaker 1
4152 #define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */
4156 #define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
4160 #define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */
4161 #define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */
4162 #define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */
4163 #define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */
4166 * R2049 (0x801) - Right PDM Speaker 1
4171 #define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */
4175 #define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
4179 #define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */
4180 #define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */
4181 #define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */
4182 #define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */
4185 * R2050 (0x802) - PDM Speaker 1 Mute Sequence
4187 #define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
4188 #define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
4189 #define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
4192 * R2056 (0x808) - Left PDM Speaker 2
4197 #define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */
4201 #define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
4205 #define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */
4206 #define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */
4207 #define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */
4208 #define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */
4211 * R2057 (0x809) - Right PDM Speaker 2
4216 #define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */
4220 #define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
4224 #define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */
4225 #define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */
4226 #define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */
4227 #define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */
4230 * R2058 (0x80A) - PDM Speaker 2 Mute Sequence
4232 #define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */
4233 #define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
4234 #define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
4246 /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
4248 WM8995_SYSCLK_MCLK1 = 1,
4255 #define WM8995_FLL1 1
4258 #define WM8995_FLL_SRC_MCLK1 1