Lines Matching +full:1 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm8962.h -- WM8962 ASoC driver
17 #define WM8962_SYSCLK_FLL 1
20 #define WM8962_FLL 1
22 #define WM8962_FLL_MCLK 1
1178 * R0 (0x00) - Left Input volume
1183 #define WM8962_IN_VU_WIDTH 1 /* IN_VU */
1187 #define WM8962_INPGAL_MUTE_WIDTH 1 /* INPGAL_MUTE */
1191 #define WM8962_INL_ZC_WIDTH 1 /* INL_ZC */
1192 #define WM8962_INL_VOL_MASK 0x003F /* INL_VOL - [5:0] */
1193 #define WM8962_INL_VOL_SHIFT 0 /* INL_VOL - [5:0] */
1194 #define WM8962_INL_VOL_WIDTH 6 /* INL_VOL - [5:0] */
1197 * R1 (0x01) - Right Input volume
1199 #define WM8962_CUST_ID_MASK 0xF000 /* CUST_ID - [15:12] */
1200 #define WM8962_CUST_ID_SHIFT 12 /* CUST_ID - [15:12] */
1201 #define WM8962_CUST_ID_WIDTH 4 /* CUST_ID - [15:12] */
1202 #define WM8962_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */
1203 #define WM8962_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */
1204 #define WM8962_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */
1208 #define WM8962_IN_VU_WIDTH 1 /* IN_VU */
1212 #define WM8962_INPGAR_MUTE_WIDTH 1 /* INPGAR_MUTE */
1216 #define WM8962_INR_ZC_WIDTH 1 /* INR_ZC */
1217 #define WM8962_INR_VOL_MASK 0x003F /* INR_VOL - [5:0] */
1218 #define WM8962_INR_VOL_SHIFT 0 /* INR_VOL - [5:0] */
1219 #define WM8962_INR_VOL_WIDTH 6 /* INR_VOL - [5:0] */
1222 * R2 (0x02) - HPOUTL volume
1227 #define WM8962_HPOUT_VU_WIDTH 1 /* HPOUT_VU */
1231 #define WM8962_HPOUTL_ZC_WIDTH 1 /* HPOUTL_ZC */
1232 #define WM8962_HPOUTL_VOL_MASK 0x007F /* HPOUTL_VOL - [6:0] */
1233 #define WM8962_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [6:0] */
1234 #define WM8962_HPOUTL_VOL_WIDTH 7 /* HPOUTL_VOL - [6:0] */
1237 * R3 (0x03) - HPOUTR volume
1242 #define WM8962_HPOUT_VU_WIDTH 1 /* HPOUT_VU */
1246 #define WM8962_HPOUTR_ZC_WIDTH 1 /* HPOUTR_ZC */
1247 #define WM8962_HPOUTR_VOL_MASK 0x007F /* HPOUTR_VOL - [6:0] */
1248 #define WM8962_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [6:0] */
1249 #define WM8962_HPOUTR_VOL_WIDTH 7 /* HPOUTR_VOL - [6:0] */
1252 * R4 (0x04) - Clocking1
1254 #define WM8962_DSPCLK_DIV_MASK 0x0600 /* DSPCLK_DIV - [10:9] */
1255 #define WM8962_DSPCLK_DIV_SHIFT 9 /* DSPCLK_DIV - [10:9] */
1256 #define WM8962_DSPCLK_DIV_WIDTH 2 /* DSPCLK_DIV - [10:9] */
1257 #define WM8962_ADCSYS_CLK_DIV_MASK 0x01C0 /* ADCSYS_CLK_DIV - [8:6] */
1258 #define WM8962_ADCSYS_CLK_DIV_SHIFT 6 /* ADCSYS_CLK_DIV - [8:6] */
1259 #define WM8962_ADCSYS_CLK_DIV_WIDTH 3 /* ADCSYS_CLK_DIV - [8:6] */
1260 #define WM8962_DACSYS_CLK_DIV_MASK 0x0038 /* DACSYS_CLK_DIV - [5:3] */
1261 #define WM8962_DACSYS_CLK_DIV_SHIFT 3 /* DACSYS_CLK_DIV - [5:3] */
1262 #define WM8962_DACSYS_CLK_DIV_WIDTH 3 /* DACSYS_CLK_DIV - [5:3] */
1263 #define WM8962_MCLKDIV_MASK 0x0006 /* MCLKDIV - [2:1] */
1264 #define WM8962_MCLKDIV_SHIFT 1 /* MCLKDIV - [2:1] */
1265 #define WM8962_MCLKDIV_WIDTH 2 /* MCLKDIV - [2:1] */
1268 * R5 (0x05) - ADC & DAC Control 1
1273 #define WM8962_ADCR_DAT_INV_WIDTH 1 /* ADCR_DAT_INV */
1277 #define WM8962_ADCL_DAT_INV_WIDTH 1 /* ADCL_DAT_INV */
1281 #define WM8962_DAC_MUTE_RAMP_WIDTH 1 /* DAC_MUTE_RAMP */
1285 #define WM8962_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
1286 #define WM8962_DAC_DEEMP_MASK 0x0006 /* DAC_DEEMP - [2:1] */
1287 #define WM8962_DAC_DEEMP_SHIFT 1 /* DAC_DEEMP - [2:1] */
1288 #define WM8962_DAC_DEEMP_WIDTH 2 /* DAC_DEEMP - [2:1] */
1292 #define WM8962_ADC_HPF_DIS_WIDTH 1 /* ADC_HPF_DIS */
1295 * R6 (0x06) - ADC & DAC Control 2
1297 #define WM8962_ADC_HPF_SR_MASK 0x3000 /* ADC_HPF_SR - [13:12] */
1298 #define WM8962_ADC_HPF_SR_SHIFT 12 /* ADC_HPF_SR - [13:12] */
1299 #define WM8962_ADC_HPF_SR_WIDTH 2 /* ADC_HPF_SR - [13:12] */
1303 #define WM8962_ADC_HPF_MODE_WIDTH 1 /* ADC_HPF_MODE */
1304 #define WM8962_ADC_HPF_CUT_MASK 0x0380 /* ADC_HPF_CUT - [9:7] */
1305 #define WM8962_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [9:7] */
1306 #define WM8962_ADC_HPF_CUT_WIDTH 3 /* ADC_HPF_CUT - [9:7] */
1310 #define WM8962_DACR_DAT_INV_WIDTH 1 /* DACR_DAT_INV */
1314 #define WM8962_DACL_DAT_INV_WIDTH 1 /* DACL_DAT_INV */
1318 #define WM8962_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */
1322 #define WM8962_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
1326 #define WM8962_DAC_HP_WIDTH 1 /* DAC_HP */
1329 * R7 (0x07) - Audio Interface 0
1334 #define WM8962_AIFDAC_TDM_MODE_WIDTH 1 /* AIFDAC_TDM_MODE */
1338 #define WM8962_AIFDAC_TDM_SLOT_WIDTH 1 /* AIFDAC_TDM_SLOT */
1342 #define WM8962_AIFADC_TDM_MODE_WIDTH 1 /* AIFADC_TDM_MODE */
1346 #define WM8962_AIFADC_TDM_SLOT_WIDTH 1 /* AIFADC_TDM_SLOT */
1350 #define WM8962_ADC_LRSWAP_WIDTH 1 /* ADC_LRSWAP */
1354 #define WM8962_BCLK_INV_WIDTH 1 /* BCLK_INV */
1358 #define WM8962_MSTR_WIDTH 1 /* MSTR */
1362 #define WM8962_DAC_LRSWAP_WIDTH 1 /* DAC_LRSWAP */
1366 #define WM8962_LRCLK_INV_WIDTH 1 /* LRCLK_INV */
1367 #define WM8962_WL_MASK 0x000C /* WL - [3:2] */
1368 #define WM8962_WL_SHIFT 2 /* WL - [3:2] */
1369 #define WM8962_WL_WIDTH 2 /* WL - [3:2] */
1370 #define WM8962_FMT_MASK 0x0003 /* FMT - [1:0] */
1371 #define WM8962_FMT_SHIFT 0 /* FMT - [1:0] */
1372 #define WM8962_FMT_WIDTH 2 /* FMT - [1:0] */
1375 * R8 (0x08) - Clocking2
1380 #define WM8962_CLKREG_OVD_WIDTH 1 /* CLKREG_OVD */
1381 #define WM8962_SYSCLK_SRC_MASK 0x0600 /* SYSCLK_SRC - [10:9] */
1382 #define WM8962_SYSCLK_SRC_SHIFT 9 /* SYSCLK_SRC - [10:9] */
1383 #define WM8962_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [10:9] */
1384 #define WM8962_CLASSD_CLK_DIV_MASK 0x01C0 /* CLASSD_CLK_DIV - [8:6] */
1385 #define WM8962_CLASSD_CLK_DIV_SHIFT 6 /* CLASSD_CLK_DIV - [8:6] */
1386 #define WM8962_CLASSD_CLK_DIV_WIDTH 3 /* CLASSD_CLK_DIV - [8:6] */
1390 #define WM8962_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
1391 #define WM8962_BCLK_DIV_MASK 0x000F /* BCLK_DIV - [3:0] */
1392 #define WM8962_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [3:0] */
1393 #define WM8962_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [3:0] */
1396 * R9 (0x09) - Audio Interface 1
1401 #define WM8962_AUTOMUTE_STS_WIDTH 1 /* AUTOMUTE_STS */
1402 #define WM8962_DAC_AUTOMUTE_SAMPLES_MASK 0x0300 /* DAC_AUTOMUTE_SAMPLES - [9:8] */
1403 #define WM8962_DAC_AUTOMUTE_SAMPLES_SHIFT 8 /* DAC_AUTOMUTE_SAMPLES - [9:8] */
1404 #define WM8962_DAC_AUTOMUTE_SAMPLES_WIDTH 2 /* DAC_AUTOMUTE_SAMPLES - [9:8] */
1408 #define WM8962_DAC_AUTOMUTE_WIDTH 1 /* DAC_AUTOMUTE */
1412 #define WM8962_DAC_COMP_WIDTH 1 /* DAC_COMP */
1416 #define WM8962_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
1420 #define WM8962_ADC_COMP_WIDTH 1 /* ADC_COMP */
1423 #define WM8962_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */
1424 #define WM8962_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
1428 #define WM8962_LOOPBACK_WIDTH 1 /* LOOPBACK */
1431 * R10 (0x0A) - Left DAC volume
1436 #define WM8962_DAC_VU_WIDTH 1 /* DAC_VU */
1437 #define WM8962_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
1438 #define WM8962_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
1439 #define WM8962_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
1442 * R11 (0x0B) - Right DAC volume
1447 #define WM8962_DAC_VU_WIDTH 1 /* DAC_VU */
1448 #define WM8962_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
1449 #define WM8962_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
1450 #define WM8962_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
1453 * R14 (0x0E) - Audio Interface 2
1455 #define WM8962_AIF_RATE_MASK 0x07FF /* AIF_RATE - [10:0] */
1456 #define WM8962_AIF_RATE_SHIFT 0 /* AIF_RATE - [10:0] */
1457 #define WM8962_AIF_RATE_WIDTH 11 /* AIF_RATE - [10:0] */
1460 * R15 (0x0F) - Software Reset
1462 #define WM8962_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
1463 #define WM8962_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
1464 #define WM8962_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
1467 * R17 (0x11) - ALC1
1472 #define WM8962_ALC_INACTIVE_ENA_WIDTH 1 /* ALC_INACTIVE_ENA */
1476 #define WM8962_ALC_LVL_MODE_WIDTH 1 /* ALC_LVL_MODE */
1480 #define WM8962_ALCL_ENA_WIDTH 1 /* ALCL_ENA */
1484 #define WM8962_ALCR_ENA_WIDTH 1 /* ALCR_ENA */
1485 #define WM8962_ALC_MAXGAIN_MASK 0x0070 /* ALC_MAXGAIN - [6:4] */
1486 #define WM8962_ALC_MAXGAIN_SHIFT 4 /* ALC_MAXGAIN - [6:4] */
1487 #define WM8962_ALC_MAXGAIN_WIDTH 3 /* ALC_MAXGAIN - [6:4] */
1488 #define WM8962_ALC_LVL_MASK 0x000F /* ALC_LVL - [3:0] */
1489 #define WM8962_ALC_LVL_SHIFT 0 /* ALC_LVL - [3:0] */
1490 #define WM8962_ALC_LVL_WIDTH 4 /* ALC_LVL - [3:0] */
1493 * R18 (0x12) - ALC2
1497 #define WM8962_ALC_LOCK_STS_SHIFT 15 /* ALC_LOCK_STS */
1498 #define WM8962_ALC_LOCK_STS_WIDTH 1 /* ALC_LOCK_STS */
1502 #define WM8962_ALC_THRESH_STS_WIDTH 1 /* ALC_THRESH_STS */
1506 #define WM8962_ALC_SAT_STS_WIDTH 1 /* ALC_SAT_STS */
1510 #define WM8962_ALC_PKOVR_STS_WIDTH 1 /* ALC_PKOVR_STS */
1514 #define WM8962_ALC_NGATE_STS_WIDTH 1 /* ALC_NGATE_STS */
1518 #define WM8962_ALC_ZC_WIDTH 1 /* ALC_ZC */
1519 #define WM8962_ALC_MINGAIN_MASK 0x0070 /* ALC_MINGAIN - [6:4] */
1520 #define WM8962_ALC_MINGAIN_SHIFT 4 /* ALC_MINGAIN - [6:4] */
1521 #define WM8962_ALC_MINGAIN_WIDTH 3 /* ALC_MINGAIN - [6:4] */
1522 #define WM8962_ALC_HLD_MASK 0x000F /* ALC_HLD - [3:0] */
1523 #define WM8962_ALC_HLD_SHIFT 0 /* ALC_HLD - [3:0] */
1524 #define WM8962_ALC_HLD_WIDTH 4 /* ALC_HLD - [3:0] */
1527 * R19 (0x13) - ALC3
1529 #define WM8962_ALC_NGATE_GAIN_MASK 0x1C00 /* ALC_NGATE_GAIN - [12:10] */
1530 #define WM8962_ALC_NGATE_GAIN_SHIFT 10 /* ALC_NGATE_GAIN - [12:10] */
1531 #define WM8962_ALC_NGATE_GAIN_WIDTH 3 /* ALC_NGATE_GAIN - [12:10] */
1535 #define WM8962_ALC_MODE_WIDTH 1 /* ALC_MODE */
1536 #define WM8962_ALC_DCY_MASK 0x00F0 /* ALC_DCY - [7:4] */
1537 #define WM8962_ALC_DCY_SHIFT 4 /* ALC_DCY - [7:4] */
1538 #define WM8962_ALC_DCY_WIDTH 4 /* ALC_DCY - [7:4] */
1539 #define WM8962_ALC_ATK_MASK 0x000F /* ALC_ATK - [3:0] */
1540 #define WM8962_ALC_ATK_SHIFT 0 /* ALC_ATK - [3:0] */
1541 #define WM8962_ALC_ATK_WIDTH 4 /* ALC_ATK - [3:0] */
1544 * R20 (0x14) - Noise Gate
1546 #define WM8962_ALC_NGATE_DCY_MASK 0xF000 /* ALC_NGATE_DCY - [15:12] */
1547 #define WM8962_ALC_NGATE_DCY_SHIFT 12 /* ALC_NGATE_DCY - [15:12] */
1548 #define WM8962_ALC_NGATE_DCY_WIDTH 4 /* ALC_NGATE_DCY - [15:12] */
1549 #define WM8962_ALC_NGATE_ATK_MASK 0x0F00 /* ALC_NGATE_ATK - [11:8] */
1550 #define WM8962_ALC_NGATE_ATK_SHIFT 8 /* ALC_NGATE_ATK - [11:8] */
1551 #define WM8962_ALC_NGATE_ATK_WIDTH 4 /* ALC_NGATE_ATK - [11:8] */
1552 #define WM8962_ALC_NGATE_THR_MASK 0x00F8 /* ALC_NGATE_THR - [7:3] */
1553 #define WM8962_ALC_NGATE_THR_SHIFT 3 /* ALC_NGATE_THR - [7:3] */
1554 #define WM8962_ALC_NGATE_THR_WIDTH 5 /* ALC_NGATE_THR - [7:3] */
1555 #define WM8962_ALC_NGATE_MODE_MASK 0x0006 /* ALC_NGATE_MODE - [2:1] */
1556 #define WM8962_ALC_NGATE_MODE_SHIFT 1 /* ALC_NGATE_MODE - [2:1] */
1557 #define WM8962_ALC_NGATE_MODE_WIDTH 2 /* ALC_NGATE_MODE - [2:1] */
1561 #define WM8962_ALC_NGATE_ENA_WIDTH 1 /* ALC_NGATE_ENA */
1564 * R21 (0x15) - Left ADC volume
1569 #define WM8962_ADC_VU_WIDTH 1 /* ADC_VU */
1570 #define WM8962_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
1571 #define WM8962_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
1572 #define WM8962_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
1575 * R22 (0x16) - Right ADC volume
1580 #define WM8962_ADC_VU_WIDTH 1 /* ADC_VU */
1581 #define WM8962_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
1582 #define WM8962_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
1583 #define WM8962_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
1586 * R23 (0x17) - Additional control(1)
1591 #define WM8962_THERR_ACT_WIDTH 1 /* THERR_ACT */
1595 #define WM8962_ADC_BIAS_WIDTH 1 /* ADC_BIAS */
1599 #define WM8962_ADC_HP_WIDTH 1 /* ADC_HP */
1603 #define WM8962_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1606 * R24 (0x18) - Additional control(2)
1611 #define WM8962_AIF_TRI_WIDTH 1 /* AIF_TRI */
1614 * R25 (0x19) - Pwr Mgmt (1)
1619 #define WM8962_DMIC_ENA_WIDTH 1 /* DMIC_ENA */
1623 #define WM8962_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
1624 #define WM8962_VMID_SEL_MASK 0x0180 /* VMID_SEL - [8:7] */
1625 #define WM8962_VMID_SEL_SHIFT 7 /* VMID_SEL - [8:7] */
1626 #define WM8962_VMID_SEL_WIDTH 2 /* VMID_SEL - [8:7] */
1630 #define WM8962_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
1634 #define WM8962_INL_ENA_WIDTH 1 /* INL_ENA */
1638 #define WM8962_INR_ENA_WIDTH 1 /* INR_ENA */
1642 #define WM8962_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
1646 #define WM8962_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
1649 #define WM8962_MICBIAS_ENA_SHIFT 1 /* MICBIAS_ENA */
1650 #define WM8962_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
1653 * R26 (0x1A) - Pwr Mgmt (2)
1658 #define WM8962_DACL_ENA_WIDTH 1 /* DACL_ENA */
1662 #define WM8962_DACR_ENA_WIDTH 1 /* DACR_ENA */
1666 #define WM8962_HPOUTL_PGA_ENA_WIDTH 1 /* HPOUTL_PGA_ENA */
1670 #define WM8962_HPOUTR_PGA_ENA_WIDTH 1 /* HPOUTR_PGA_ENA */
1674 #define WM8962_SPKOUTL_PGA_ENA_WIDTH 1 /* SPKOUTL_PGA_ENA */
1678 #define WM8962_SPKOUTR_PGA_ENA_WIDTH 1 /* SPKOUTR_PGA_ENA */
1681 #define WM8962_HPOUTL_PGA_MUTE_SHIFT 1 /* HPOUTL_PGA_MUTE */
1682 #define WM8962_HPOUTL_PGA_MUTE_WIDTH 1 /* HPOUTL_PGA_MUTE */
1686 #define WM8962_HPOUTR_PGA_MUTE_WIDTH 1 /* HPOUTR_PGA_MUTE */
1689 * R27 (0x1B) - Additional Control (3)
1694 #define WM8962_SAMPLE_RATE_INT_MODE_WIDTH 1 /* SAMPLE_RATE_INT_MODE */
1695 #define WM8962_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */
1696 #define WM8962_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */
1697 #define WM8962_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */
1700 * R28 (0x1C) - Anti-pop
1705 #define WM8962_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
1709 #define WM8962_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
1713 #define WM8962_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
1716 * R30 (0x1E) - Clocking 3
1718 #define WM8962_DBCLK_DIV_MASK 0xE000 /* DBCLK_DIV - [15:13] */
1719 #define WM8962_DBCLK_DIV_SHIFT 13 /* DBCLK_DIV - [15:13] */
1720 #define WM8962_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [15:13] */
1721 #define WM8962_OPCLK_DIV_MASK 0x1C00 /* OPCLK_DIV - [12:10] */
1722 #define WM8962_OPCLK_DIV_SHIFT 10 /* OPCLK_DIV - [12:10] */
1723 #define WM8962_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [12:10] */
1724 #define WM8962_TOCLK_DIV_MASK 0x0380 /* TOCLK_DIV - [9:7] */
1725 #define WM8962_TOCLK_DIV_SHIFT 7 /* TOCLK_DIV - [9:7] */
1726 #define WM8962_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [9:7] */
1727 #define WM8962_F256KCLK_DIV_MASK 0x007E /* F256KCLK_DIV - [6:1] */
1728 #define WM8962_F256KCLK_DIV_SHIFT 1 /* F256KCLK_DIV - [6:1] */
1729 #define WM8962_F256KCLK_DIV_WIDTH 6 /* F256KCLK_DIV - [6:1] */
1732 * R31 (0x1F) - Input mixer control (1)
1737 #define WM8962_MIXINL_MUTE_WIDTH 1 /* MIXINL_MUTE */
1741 #define WM8962_MIXINR_MUTE_WIDTH 1 /* MIXINR_MUTE */
1744 #define WM8962_MIXINL_ENA_SHIFT 1 /* MIXINL_ENA */
1745 #define WM8962_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */
1749 #define WM8962_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */
1752 * R32 (0x20) - Left input mixer volume
1754 #define WM8962_IN2L_MIXINL_VOL_MASK 0x01C0 /* IN2L_MIXINL_VOL - [8:6] */
1755 #define WM8962_IN2L_MIXINL_VOL_SHIFT 6 /* IN2L_MIXINL_VOL - [8:6] */
1756 #define WM8962_IN2L_MIXINL_VOL_WIDTH 3 /* IN2L_MIXINL_VOL - [8:6] */
1757 #define WM8962_INPGAL_MIXINL_VOL_MASK 0x0038 /* INPGAL_MIXINL_VOL - [5:3] */
1758 #define WM8962_INPGAL_MIXINL_VOL_SHIFT 3 /* INPGAL_MIXINL_VOL - [5:3] */
1759 #define WM8962_INPGAL_MIXINL_VOL_WIDTH 3 /* INPGAL_MIXINL_VOL - [5:3] */
1760 #define WM8962_IN3L_MIXINL_VOL_MASK 0x0007 /* IN3L_MIXINL_VOL - [2:0] */
1761 #define WM8962_IN3L_MIXINL_VOL_SHIFT 0 /* IN3L_MIXINL_VOL - [2:0] */
1762 #define WM8962_IN3L_MIXINL_VOL_WIDTH 3 /* IN3L_MIXINL_VOL - [2:0] */
1765 * R33 (0x21) - Right input mixer volume
1767 #define WM8962_IN2R_MIXINR_VOL_MASK 0x01C0 /* IN2R_MIXINR_VOL - [8:6] */
1768 #define WM8962_IN2R_MIXINR_VOL_SHIFT 6 /* IN2R_MIXINR_VOL - [8:6] */
1769 #define WM8962_IN2R_MIXINR_VOL_WIDTH 3 /* IN2R_MIXINR_VOL - [8:6] */
1770 #define WM8962_INPGAR_MIXINR_VOL_MASK 0x0038 /* INPGAR_MIXINR_VOL - [5:3] */
1771 #define WM8962_INPGAR_MIXINR_VOL_SHIFT 3 /* INPGAR_MIXINR_VOL - [5:3] */
1772 #define WM8962_INPGAR_MIXINR_VOL_WIDTH 3 /* INPGAR_MIXINR_VOL - [5:3] */
1773 #define WM8962_IN3R_MIXINR_VOL_MASK 0x0007 /* IN3R_MIXINR_VOL - [2:0] */
1774 #define WM8962_IN3R_MIXINR_VOL_SHIFT 0 /* IN3R_MIXINR_VOL - [2:0] */
1775 #define WM8962_IN3R_MIXINR_VOL_WIDTH 3 /* IN3R_MIXINR_VOL - [2:0] */
1778 * R34 (0x22) - Input mixer control (2)
1783 #define WM8962_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */
1787 #define WM8962_IN3L_TO_MIXINL_WIDTH 1 /* IN3L_TO_MIXINL */
1791 #define WM8962_INPGAL_TO_MIXINL_WIDTH 1 /* INPGAL_TO_MIXINL */
1795 #define WM8962_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */
1798 #define WM8962_IN3R_TO_MIXINR_SHIFT 1 /* IN3R_TO_MIXINR */
1799 #define WM8962_IN3R_TO_MIXINR_WIDTH 1 /* IN3R_TO_MIXINR */
1803 #define WM8962_INPGAR_TO_MIXINR_WIDTH 1 /* INPGAR_TO_MIXINR */
1806 * R35 (0x23) - Input bias control
1808 #define WM8962_MIXIN_BIAS_MASK 0x0038 /* MIXIN_BIAS - [5:3] */
1809 #define WM8962_MIXIN_BIAS_SHIFT 3 /* MIXIN_BIAS - [5:3] */
1810 #define WM8962_MIXIN_BIAS_WIDTH 3 /* MIXIN_BIAS - [5:3] */
1811 #define WM8962_INPGA_BIAS_MASK 0x0007 /* INPGA_BIAS - [2:0] */
1812 #define WM8962_INPGA_BIAS_SHIFT 0 /* INPGA_BIAS - [2:0] */
1813 #define WM8962_INPGA_BIAS_WIDTH 3 /* INPGA_BIAS - [2:0] */
1816 * R37 (0x25) - Left input PGA control
1821 #define WM8962_INPGAL_ENA_WIDTH 1 /* INPGAL_ENA */
1825 #define WM8962_IN1L_TO_INPGAL_WIDTH 1 /* IN1L_TO_INPGAL */
1829 #define WM8962_IN2L_TO_INPGAL_WIDTH 1 /* IN2L_TO_INPGAL */
1832 #define WM8962_IN3L_TO_INPGAL_SHIFT 1 /* IN3L_TO_INPGAL */
1833 #define WM8962_IN3L_TO_INPGAL_WIDTH 1 /* IN3L_TO_INPGAL */
1837 #define WM8962_IN4L_TO_INPGAL_WIDTH 1 /* IN4L_TO_INPGAL */
1840 * R38 (0x26) - Right input PGA control
1845 #define WM8962_INPGAR_ENA_WIDTH 1 /* INPGAR_ENA */
1849 #define WM8962_IN1R_TO_INPGAR_WIDTH 1 /* IN1R_TO_INPGAR */
1853 #define WM8962_IN2R_TO_INPGAR_WIDTH 1 /* IN2R_TO_INPGAR */
1856 #define WM8962_IN3R_TO_INPGAR_SHIFT 1 /* IN3R_TO_INPGAR */
1857 #define WM8962_IN3R_TO_INPGAR_WIDTH 1 /* IN3R_TO_INPGAR */
1861 #define WM8962_IN4R_TO_INPGAR_WIDTH 1 /* IN4R_TO_INPGAR */
1864 * R40 (0x28) - SPKOUTL volume
1869 #define WM8962_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */
1873 #define WM8962_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */
1874 #define WM8962_SPKOUTL_VOL_MASK 0x007F /* SPKOUTL_VOL - [6:0] */
1875 #define WM8962_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [6:0] */
1876 #define WM8962_SPKOUTL_VOL_WIDTH 7 /* SPKOUTL_VOL - [6:0] */
1879 * R41 (0x29) - SPKOUTR volume
1884 #define WM8962_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */
1885 #define WM8962_SPKOUTR_VOL_MASK 0x007F /* SPKOUTR_VOL - [6:0] */
1886 #define WM8962_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [6:0] */
1887 #define WM8962_SPKOUTR_VOL_WIDTH 7 /* SPKOUTR_VOL - [6:0] */
1890 * R47 (0x2F) - Thermal Shutdown Status
1895 #define WM8962_TEMP_ERR_HP_WIDTH 1 /* TEMP_ERR_HP */
1899 #define WM8962_TEMP_WARN_HP_WIDTH 1 /* TEMP_WARN_HP */
1902 #define WM8962_TEMP_ERR_SPK_SHIFT 1 /* TEMP_ERR_SPK */
1903 #define WM8962_TEMP_ERR_SPK_WIDTH 1 /* TEMP_ERR_SPK */
1907 #define WM8962_TEMP_WARN_SPK_WIDTH 1 /* TEMP_WARN_SPK */
1910 * R48 (0x30) - Additional Control (4)
1912 #define WM8962_MICDET_THR_MASK 0x7000 /* MICDET_THR - [14:12] */
1913 #define WM8962_MICDET_THR_SHIFT 12 /* MICDET_THR - [14:12] */
1914 #define WM8962_MICDET_THR_WIDTH 3 /* MICDET_THR - [14:12] */
1915 #define WM8962_MICSHORT_THR_MASK 0x0C00 /* MICSHORT_THR - [11:10] */
1916 #define WM8962_MICSHORT_THR_SHIFT 10 /* MICSHORT_THR - [11:10] */
1917 #define WM8962_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [11:10] */
1921 #define WM8962_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
1925 #define WM8962_MICDET_STS_WIDTH 1 /* MICDET_STS */
1929 #define WM8962_MICSHORT_STS_WIDTH 1 /* MICSHORT_STS */
1933 #define WM8962_TEMP_ENA_HP_WIDTH 1 /* TEMP_ENA_HP */
1936 #define WM8962_TEMP_ENA_SPK_SHIFT 1 /* TEMP_ENA_SPK */
1937 #define WM8962_TEMP_ENA_SPK_WIDTH 1 /* TEMP_ENA_SPK */
1941 #define WM8962_MICBIAS_LVL_WIDTH 1 /* MICBIAS_LVL */
1944 * R49 (0x31) - Class D Control 1
1949 #define WM8962_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */
1953 #define WM8962_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
1957 #define WM8962_DAC_MUTE_ALT_WIDTH 1 /* DAC_MUTE */
1960 #define WM8962_SPKOUTL_PGA_MUTE_SHIFT 1 /* SPKOUTL_PGA_MUTE */
1961 #define WM8962_SPKOUTL_PGA_MUTE_WIDTH 1 /* SPKOUTL_PGA_MUTE */
1965 #define WM8962_SPKOUTR_PGA_MUTE_WIDTH 1 /* SPKOUTR_PGA_MUTE */
1968 * R51 (0x33) - Class D Control 2
1973 #define WM8962_SPK_MONO_WIDTH 1 /* SPK_MONO */
1974 #define WM8962_CLASSD_VOL_MASK 0x0007 /* CLASSD_VOL - [2:0] */
1975 #define WM8962_CLASSD_VOL_SHIFT 0 /* CLASSD_VOL - [2:0] */
1976 #define WM8962_CLASSD_VOL_WIDTH 3 /* CLASSD_VOL - [2:0] */
1979 * R56 (0x38) - Clocking 4
1981 #define WM8962_SYSCLK_RATE_MASK 0x001E /* SYSCLK_RATE - [4:1] */
1982 #define WM8962_SYSCLK_RATE_SHIFT 1 /* SYSCLK_RATE - [4:1] */
1983 #define WM8962_SYSCLK_RATE_WIDTH 4 /* SYSCLK_RATE - [4:1] */
1986 * R57 (0x39) - DAC DSP Mixing (1)
1991 #define WM8962_DAC_MONOMIX_WIDTH 1 /* DAC_MONOMIX */
1992 #define WM8962_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */
1993 #define WM8962_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */
1994 #define WM8962_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */
1995 #define WM8962_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */
1996 #define WM8962_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */
1997 #define WM8962_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */
2000 * R58 (0x3A) - DAC DSP Mixing (2)
2002 #define WM8962_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */
2003 #define WM8962_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */
2004 #define WM8962_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */
2005 #define WM8962_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
2006 #define WM8962_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
2007 #define WM8962_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
2010 * R60 (0x3C) - DC Servo 0
2015 #define WM8962_INL_DCS_ENA_WIDTH 1 /* INL_DCS_ENA */
2019 #define WM8962_INL_DCS_STARTUP_WIDTH 1 /* INL_DCS_STARTUP */
2023 #define WM8962_INR_DCS_ENA_WIDTH 1 /* INR_DCS_ENA */
2027 #define WM8962_INR_DCS_STARTUP_WIDTH 1 /* INR_DCS_STARTUP */
2030 * R61 (0x3D) - DC Servo 1
2035 #define WM8962_HP1L_DCS_ENA_WIDTH 1 /* HP1L_DCS_ENA */
2039 #define WM8962_HP1L_DCS_STARTUP_WIDTH 1 /* HP1L_DCS_STARTUP */
2043 #define WM8962_HP1L_DCS_SYNC_WIDTH 1 /* HP1L_DCS_SYNC */
2047 #define WM8962_HP1R_DCS_ENA_WIDTH 1 /* HP1R_DCS_ENA */
2051 #define WM8962_HP1R_DCS_STARTUP_WIDTH 1 /* HP1R_DCS_STARTUP */
2055 #define WM8962_HP1R_DCS_SYNC_WIDTH 1 /* HP1R_DCS_SYNC */
2058 * R64 (0x40) - DC Servo 4
2060 #define WM8962_HP1_DCS_SYNC_STEPS_MASK 0x3F80 /* HP1_DCS_SYNC_STEPS - [13:7] */
2061 #define WM8962_HP1_DCS_SYNC_STEPS_SHIFT 7 /* HP1_DCS_SYNC_STEPS - [13:7] */
2062 #define WM8962_HP1_DCS_SYNC_STEPS_WIDTH 7 /* HP1_DCS_SYNC_STEPS - [13:7] */
2065 * R66 (0x42) - DC Servo 6
2070 #define WM8962_DCS_STARTUP_DONE_INL_WIDTH 1 /* DCS_STARTUP_DONE_INL */
2074 #define WM8962_DCS_STARTUP_DONE_INR_WIDTH 1 /* DCS_STARTUP_DONE_INR */
2078 #define WM8962_DCS_STARTUP_DONE_HP1L_WIDTH 1 /* DCS_STARTUP_DONE_HP1L */
2082 #define WM8962_DCS_STARTUP_DONE_HP1R_WIDTH 1 /* DCS_STARTUP_DONE_HP1R */
2085 * R68 (0x44) - Analogue PGA Bias
2087 #define WM8962_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */
2088 #define WM8962_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */
2089 #define WM8962_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */
2092 * R69 (0x45) - Analogue HP 0
2097 #define WM8962_HP1L_RMV_SHORT_WIDTH 1 /* HP1L_RMV_SHORT */
2101 #define WM8962_HP1L_ENA_OUTP_WIDTH 1 /* HP1L_ENA_OUTP */
2105 #define WM8962_HP1L_ENA_DLY_WIDTH 1 /* HP1L_ENA_DLY */
2109 #define WM8962_HP1L_ENA_WIDTH 1 /* HP1L_ENA */
2113 #define WM8962_HP1R_RMV_SHORT_WIDTH 1 /* HP1R_RMV_SHORT */
2117 #define WM8962_HP1R_ENA_OUTP_WIDTH 1 /* HP1R_ENA_OUTP */
2120 #define WM8962_HP1R_ENA_DLY_SHIFT 1 /* HP1R_ENA_DLY */
2121 #define WM8962_HP1R_ENA_DLY_WIDTH 1 /* HP1R_ENA_DLY */
2125 #define WM8962_HP1R_ENA_WIDTH 1 /* HP1R_ENA */
2128 * R71 (0x47) - Analogue HP 2
2130 #define WM8962_HP1L_VOL_MASK 0x01C0 /* HP1L_VOL - [8:6] */
2131 #define WM8962_HP1L_VOL_SHIFT 6 /* HP1L_VOL - [8:6] */
2132 #define WM8962_HP1L_VOL_WIDTH 3 /* HP1L_VOL - [8:6] */
2133 #define WM8962_HP1R_VOL_MASK 0x0038 /* HP1R_VOL - [5:3] */
2134 #define WM8962_HP1R_VOL_SHIFT 3 /* HP1R_VOL - [5:3] */
2135 #define WM8962_HP1R_VOL_WIDTH 3 /* HP1R_VOL - [5:3] */
2136 #define WM8962_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */
2137 #define WM8962_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */
2138 #define WM8962_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */
2141 * R72 (0x48) - Charge Pump 1
2146 #define WM8962_CP_ENA_WIDTH 1 /* CP_ENA */
2149 * R82 (0x52) - Charge Pump B
2154 #define WM8962_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
2157 * R87 (0x57) - Write Sequencer Control 1
2162 #define WM8962_WSEQ_AUTOSEQ_ENA_WIDTH 1 /* WSEQ_AUTOSEQ_ENA */
2166 #define WM8962_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
2169 * R90 (0x5A) - Write Sequencer Control 2
2174 #define WM8962_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
2178 #define WM8962_WSEQ_START_WIDTH 1 /* WSEQ_START */
2179 #define WM8962_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
2180 #define WM8962_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
2181 #define WM8962_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
2184 * R93 (0x5D) - Write Sequencer Control 3
2186 #define WM8962_WSEQ_CURRENT_INDEX_MASK 0x03F8 /* WSEQ_CURRENT_INDEX - [9:3] */
2187 #define WM8962_WSEQ_CURRENT_INDEX_SHIFT 3 /* WSEQ_CURRENT_INDEX - [9:3] */
2188 #define WM8962_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [9:3] */
2192 #define WM8962_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
2195 * R94 (0x5E) - Control Interface
2200 #define WM8962_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
2204 #define WM8962_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
2208 #define WM8962_SPI_CFG_WIDTH 1 /* SPI_CFG */
2211 * R99 (0x63) - Mixer Enables
2216 #define WM8962_HPMIXL_ENA_WIDTH 1 /* HPMIXL_ENA */
2220 #define WM8962_HPMIXR_ENA_WIDTH 1 /* HPMIXR_ENA */
2223 #define WM8962_SPKMIXL_ENA_SHIFT 1 /* SPKMIXL_ENA */
2224 #define WM8962_SPKMIXL_ENA_WIDTH 1 /* SPKMIXL_ENA */
2228 #define WM8962_SPKMIXR_ENA_WIDTH 1 /* SPKMIXR_ENA */
2231 * R100 (0x64) - Headphone Mixer (1)
2236 #define WM8962_HPMIXL_TO_HPOUTL_PGA_WIDTH 1 /* HPMIXL_TO_HPOUTL_PGA */
2240 #define WM8962_DACL_TO_HPMIXL_WIDTH 1 /* DACL_TO_HPMIXL */
2244 #define WM8962_DACR_TO_HPMIXL_WIDTH 1 /* DACR_TO_HPMIXL */
2248 #define WM8962_MIXINL_TO_HPMIXL_WIDTH 1 /* MIXINL_TO_HPMIXL */
2252 #define WM8962_MIXINR_TO_HPMIXL_WIDTH 1 /* MIXINR_TO_HPMIXL */
2255 #define WM8962_IN4L_TO_HPMIXL_SHIFT 1 /* IN4L_TO_HPMIXL */
2256 #define WM8962_IN4L_TO_HPMIXL_WIDTH 1 /* IN4L_TO_HPMIXL */
2260 #define WM8962_IN4R_TO_HPMIXL_WIDTH 1 /* IN4R_TO_HPMIXL */
2263 * R101 (0x65) - Headphone Mixer (2)
2268 #define WM8962_HPMIXR_TO_HPOUTR_PGA_WIDTH 1 /* HPMIXR_TO_HPOUTR_PGA */
2272 #define WM8962_DACL_TO_HPMIXR_WIDTH 1 /* DACL_TO_HPMIXR */
2276 #define WM8962_DACR_TO_HPMIXR_WIDTH 1 /* DACR_TO_HPMIXR */
2280 #define WM8962_MIXINL_TO_HPMIXR_WIDTH 1 /* MIXINL_TO_HPMIXR */
2284 #define WM8962_MIXINR_TO_HPMIXR_WIDTH 1 /* MIXINR_TO_HPMIXR */
2287 #define WM8962_IN4L_TO_HPMIXR_SHIFT 1 /* IN4L_TO_HPMIXR */
2288 #define WM8962_IN4L_TO_HPMIXR_WIDTH 1 /* IN4L_TO_HPMIXR */
2292 #define WM8962_IN4R_TO_HPMIXR_WIDTH 1 /* IN4R_TO_HPMIXR */
2295 * R102 (0x66) - Headphone Mixer (3)
2300 #define WM8962_HPMIXL_MUTE_WIDTH 1 /* HPMIXL_MUTE */
2304 #define WM8962_MIXINL_HPMIXL_VOL_WIDTH 1 /* MIXINL_HPMIXL_VOL */
2308 #define WM8962_MIXINR_HPMIXL_VOL_WIDTH 1 /* MIXINR_HPMIXL_VOL */
2309 #define WM8962_IN4L_HPMIXL_VOL_MASK 0x0038 /* IN4L_HPMIXL_VOL - [5:3] */
2310 #define WM8962_IN4L_HPMIXL_VOL_SHIFT 3 /* IN4L_HPMIXL_VOL - [5:3] */
2311 #define WM8962_IN4L_HPMIXL_VOL_WIDTH 3 /* IN4L_HPMIXL_VOL - [5:3] */
2312 #define WM8962_IN4R_HPMIXL_VOL_MASK 0x0007 /* IN4R_HPMIXL_VOL - [2:0] */
2313 #define WM8962_IN4R_HPMIXL_VOL_SHIFT 0 /* IN4R_HPMIXL_VOL - [2:0] */
2314 #define WM8962_IN4R_HPMIXL_VOL_WIDTH 3 /* IN4R_HPMIXL_VOL - [2:0] */
2317 * R103 (0x67) - Headphone Mixer (4)
2322 #define WM8962_HPMIXR_MUTE_WIDTH 1 /* HPMIXR_MUTE */
2326 #define WM8962_MIXINL_HPMIXR_VOL_WIDTH 1 /* MIXINL_HPMIXR_VOL */
2330 #define WM8962_MIXINR_HPMIXR_VOL_WIDTH 1 /* MIXINR_HPMIXR_VOL */
2331 #define WM8962_IN4L_HPMIXR_VOL_MASK 0x0038 /* IN4L_HPMIXR_VOL - [5:3] */
2332 #define WM8962_IN4L_HPMIXR_VOL_SHIFT 3 /* IN4L_HPMIXR_VOL - [5:3] */
2333 #define WM8962_IN4L_HPMIXR_VOL_WIDTH 3 /* IN4L_HPMIXR_VOL - [5:3] */
2334 #define WM8962_IN4R_HPMIXR_VOL_MASK 0x0007 /* IN4R_HPMIXR_VOL - [2:0] */
2335 #define WM8962_IN4R_HPMIXR_VOL_SHIFT 0 /* IN4R_HPMIXR_VOL - [2:0] */
2336 #define WM8962_IN4R_HPMIXR_VOL_WIDTH 3 /* IN4R_HPMIXR_VOL - [2:0] */
2339 * R105 (0x69) - Speaker Mixer (1)
2344 #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_WIDTH 1 /* SPKMIXL_TO_SPKOUTL_PGA */
2348 #define WM8962_DACL_TO_SPKMIXL_WIDTH 1 /* DACL_TO_SPKMIXL */
2352 #define WM8962_DACR_TO_SPKMIXL_WIDTH 1 /* DACR_TO_SPKMIXL */
2356 #define WM8962_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */
2360 #define WM8962_MIXINR_TO_SPKMIXL_WIDTH 1 /* MIXINR_TO_SPKMIXL */
2363 #define WM8962_IN4L_TO_SPKMIXL_SHIFT 1 /* IN4L_TO_SPKMIXL */
2364 #define WM8962_IN4L_TO_SPKMIXL_WIDTH 1 /* IN4L_TO_SPKMIXL */
2368 #define WM8962_IN4R_TO_SPKMIXL_WIDTH 1 /* IN4R_TO_SPKMIXL */
2371 * R106 (0x6A) - Speaker Mixer (2)
2376 #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_WIDTH 1 /* SPKMIXR_TO_SPKOUTR_PGA */
2380 #define WM8962_DACL_TO_SPKMIXR_WIDTH 1 /* DACL_TO_SPKMIXR */
2384 #define WM8962_DACR_TO_SPKMIXR_WIDTH 1 /* DACR_TO_SPKMIXR */
2388 #define WM8962_MIXINL_TO_SPKMIXR_WIDTH 1 /* MIXINL_TO_SPKMIXR */
2392 #define WM8962_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */
2395 #define WM8962_IN4L_TO_SPKMIXR_SHIFT 1 /* IN4L_TO_SPKMIXR */
2396 #define WM8962_IN4L_TO_SPKMIXR_WIDTH 1 /* IN4L_TO_SPKMIXR */
2400 #define WM8962_IN4R_TO_SPKMIXR_WIDTH 1 /* IN4R_TO_SPKMIXR */
2403 * R107 (0x6B) - Speaker Mixer (3)
2408 #define WM8962_SPKMIXL_MUTE_WIDTH 1 /* SPKMIXL_MUTE */
2412 #define WM8962_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */
2416 #define WM8962_MIXINR_SPKMIXL_VOL_WIDTH 1 /* MIXINR_SPKMIXL_VOL */
2417 #define WM8962_IN4L_SPKMIXL_VOL_MASK 0x0038 /* IN4L_SPKMIXL_VOL - [5:3] */
2418 #define WM8962_IN4L_SPKMIXL_VOL_SHIFT 3 /* IN4L_SPKMIXL_VOL - [5:3] */
2419 #define WM8962_IN4L_SPKMIXL_VOL_WIDTH 3 /* IN4L_SPKMIXL_VOL - [5:3] */
2420 #define WM8962_IN4R_SPKMIXL_VOL_MASK 0x0007 /* IN4R_SPKMIXL_VOL - [2:0] */
2421 #define WM8962_IN4R_SPKMIXL_VOL_SHIFT 0 /* IN4R_SPKMIXL_VOL - [2:0] */
2422 #define WM8962_IN4R_SPKMIXL_VOL_WIDTH 3 /* IN4R_SPKMIXL_VOL - [2:0] */
2425 * R108 (0x6C) - Speaker Mixer (4)
2430 #define WM8962_SPKMIXR_MUTE_WIDTH 1 /* SPKMIXR_MUTE */
2434 #define WM8962_MIXINL_SPKMIXR_VOL_WIDTH 1 /* MIXINL_SPKMIXR_VOL */
2438 #define WM8962_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */
2439 #define WM8962_IN4L_SPKMIXR_VOL_MASK 0x0038 /* IN4L_SPKMIXR_VOL - [5:3] */
2440 #define WM8962_IN4L_SPKMIXR_VOL_SHIFT 3 /* IN4L_SPKMIXR_VOL - [5:3] */
2441 #define WM8962_IN4L_SPKMIXR_VOL_WIDTH 3 /* IN4L_SPKMIXR_VOL - [5:3] */
2442 #define WM8962_IN4R_SPKMIXR_VOL_MASK 0x0007 /* IN4R_SPKMIXR_VOL - [2:0] */
2443 #define WM8962_IN4R_SPKMIXR_VOL_SHIFT 0 /* IN4R_SPKMIXR_VOL - [2:0] */
2444 #define WM8962_IN4R_SPKMIXR_VOL_WIDTH 3 /* IN4R_SPKMIXR_VOL - [2:0] */
2447 * R109 (0x6D) - Speaker Mixer (5)
2452 #define WM8962_DACL_SPKMIXL_VOL_WIDTH 1 /* DACL_SPKMIXL_VOL */
2456 #define WM8962_DACR_SPKMIXL_VOL_WIDTH 1 /* DACR_SPKMIXL_VOL */
2460 #define WM8962_DACL_SPKMIXR_VOL_WIDTH 1 /* DACL_SPKMIXR_VOL */
2464 #define WM8962_DACR_SPKMIXR_VOL_WIDTH 1 /* DACR_SPKMIXR_VOL */
2467 * R110 (0x6E) - Beep Generator (1)
2469 #define WM8962_BEEP_GAIN_MASK 0x00F0 /* BEEP_GAIN - [7:4] */
2470 #define WM8962_BEEP_GAIN_SHIFT 4 /* BEEP_GAIN - [7:4] */
2471 #define WM8962_BEEP_GAIN_WIDTH 4 /* BEEP_GAIN - [7:4] */
2472 #define WM8962_BEEP_RATE_MASK 0x0006 /* BEEP_RATE - [2:1] */
2473 #define WM8962_BEEP_RATE_SHIFT 1 /* BEEP_RATE - [2:1] */
2474 #define WM8962_BEEP_RATE_WIDTH 2 /* BEEP_RATE - [2:1] */
2478 #define WM8962_BEEP_ENA_WIDTH 1 /* BEEP_ENA */
2481 * R115 (0x73) - Oscillator Trim (3)
2483 #define WM8962_OSC_TRIM_XTI_MASK 0x001F /* OSC_TRIM_XTI - [4:0] */
2484 #define WM8962_OSC_TRIM_XTI_SHIFT 0 /* OSC_TRIM_XTI - [4:0] */
2485 #define WM8962_OSC_TRIM_XTI_WIDTH 5 /* OSC_TRIM_XTI - [4:0] */
2488 * R116 (0x74) - Oscillator Trim (4)
2490 #define WM8962_OSC_TRIM_XTO_MASK 0x001F /* OSC_TRIM_XTO - [4:0] */
2491 #define WM8962_OSC_TRIM_XTO_SHIFT 0 /* OSC_TRIM_XTO - [4:0] */
2492 #define WM8962_OSC_TRIM_XTO_WIDTH 5 /* OSC_TRIM_XTO - [4:0] */
2495 * R119 (0x77) - Oscillator Trim (7)
2497 #define WM8962_XTO_CAP_SEL_MASK 0x00F0 /* XTO_CAP_SEL - [7:4] */
2498 #define WM8962_XTO_CAP_SEL_SHIFT 4 /* XTO_CAP_SEL - [7:4] */
2499 #define WM8962_XTO_CAP_SEL_WIDTH 4 /* XTO_CAP_SEL - [7:4] */
2500 #define WM8962_XTI_CAP_SEL_MASK 0x000F /* XTI_CAP_SEL - [3:0] */
2501 #define WM8962_XTI_CAP_SEL_SHIFT 0 /* XTI_CAP_SEL - [3:0] */
2502 #define WM8962_XTI_CAP_SEL_WIDTH 4 /* XTI_CAP_SEL - [3:0] */
2505 * R124 (0x7C) - Analogue Clocking1
2507 #define WM8962_CLKOUT2_SEL_MASK 0x0060 /* CLKOUT2_SEL - [6:5] */
2508 #define WM8962_CLKOUT2_SEL_SHIFT 5 /* CLKOUT2_SEL - [6:5] */
2509 #define WM8962_CLKOUT2_SEL_WIDTH 2 /* CLKOUT2_SEL - [6:5] */
2510 #define WM8962_CLKOUT3_SEL_MASK 0x0018 /* CLKOUT3_SEL - [4:3] */
2511 #define WM8962_CLKOUT3_SEL_SHIFT 3 /* CLKOUT3_SEL - [4:3] */
2512 #define WM8962_CLKOUT3_SEL_WIDTH 2 /* CLKOUT3_SEL - [4:3] */
2516 #define WM8962_CLKOUT5_SEL_WIDTH 1 /* CLKOUT5_SEL */
2519 * R125 (0x7D) - Analogue Clocking2
2524 #define WM8962_PLL2_OUTDIV_WIDTH 1 /* PLL2_OUTDIV */
2528 #define WM8962_PLL3_OUTDIV_WIDTH 1 /* PLL3_OUTDIV */
2529 #define WM8962_PLL_SYSCLK_DIV_MASK 0x0018 /* PLL_SYSCLK_DIV - [4:3] */
2530 #define WM8962_PLL_SYSCLK_DIV_SHIFT 3 /* PLL_SYSCLK_DIV - [4:3] */
2531 #define WM8962_PLL_SYSCLK_DIV_WIDTH 2 /* PLL_SYSCLK_DIV - [4:3] */
2535 #define WM8962_CLKOUT3_DIV_WIDTH 1 /* CLKOUT3_DIV */
2538 #define WM8962_CLKOUT2_DIV_SHIFT 1 /* CLKOUT2_DIV */
2539 #define WM8962_CLKOUT2_DIV_WIDTH 1 /* CLKOUT2_DIV */
2543 #define WM8962_CLKOUT5_DIV_WIDTH 1 /* CLKOUT5_DIV */
2546 * R126 (0x7E) - Analogue Clocking3
2551 #define WM8962_CLKOUT2_OE_WIDTH 1 /* CLKOUT2_OE */
2555 #define WM8962_CLKOUT3_OE_WIDTH 1 /* CLKOUT3_OE */
2559 #define WM8962_CLKOUT5_OE_WIDTH 1 /* CLKOUT5_OE */
2562 * R127 (0x7F) - PLL Software Reset
2564 #define WM8962_SW_RESET_PLL_MASK 0xFFFF /* SW_RESET_PLL - [15:0] */
2565 #define WM8962_SW_RESET_PLL_SHIFT 0 /* SW_RESET_PLL - [15:0] */
2566 #define WM8962_SW_RESET_PLL_WIDTH 16 /* SW_RESET_PLL - [15:0] */
2569 * R129 (0x81) - PLL2
2574 #define WM8962_OSC_ENA_WIDTH 1 /* OSC_ENA */
2578 #define WM8962_PLL2_ENA_WIDTH 1 /* PLL2_ENA */
2582 #define WM8962_PLL3_ENA_WIDTH 1 /* PLL3_ENA */
2585 * R131 (0x83) - PLL 4
2589 #define WM8962_PLL_CLK_SRC_SHIFT 1 /* PLL_CLK_SRC */
2590 #define WM8962_PLL_CLK_SRC_WIDTH 1 /* PLL_CLK_SRC */
2594 #define WM8962_FLL_TO_PLL3_WIDTH 1 /* FLL_TO_PLL3 */
2597 * R136 (0x88) - PLL 9
2602 #define WM8962_PLL2_FRAC_WIDTH 1 /* PLL2_FRAC */
2603 #define WM8962_PLL2_N_MASK 0x001F /* PLL2_N - [4:0] */
2604 #define WM8962_PLL2_N_SHIFT 0 /* PLL2_N - [4:0] */
2605 #define WM8962_PLL2_N_WIDTH 5 /* PLL2_N - [4:0] */
2608 * R137 (0x89) - PLL 10
2610 #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */
2611 #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */
2612 #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */
2615 * R138 (0x8A) - PLL 11
2617 #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */
2618 #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */
2619 #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */
2622 * R139 (0x8B) - PLL 12
2624 #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */
2625 #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */
2626 #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */
2629 * R140 (0x8C) - PLL 13
2634 #define WM8962_PLL3_FRAC_WIDTH 1 /* PLL3_FRAC */
2635 #define WM8962_PLL3_N_MASK 0x001F /* PLL3_N - [4:0] */
2636 #define WM8962_PLL3_N_SHIFT 0 /* PLL3_N - [4:0] */
2637 #define WM8962_PLL3_N_WIDTH 5 /* PLL3_N - [4:0] */
2640 * R141 (0x8D) - PLL 14
2642 #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */
2643 #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */
2644 #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */
2647 * R142 (0x8E) - PLL 15
2649 #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */
2650 #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */
2651 #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */
2654 * R143 (0x8F) - PLL 16
2656 #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */
2657 #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */
2658 #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */
2661 * R155 (0x9B) - FLL Control (1)
2663 #define WM8962_FLL_REFCLK_SRC_MASK 0x0060 /* FLL_REFCLK_SRC - [6:5] */
2664 #define WM8962_FLL_REFCLK_SRC_SHIFT 5 /* FLL_REFCLK_SRC - [6:5] */
2665 #define WM8962_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [6:5] */
2669 #define WM8962_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
2672 #define WM8962_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
2673 #define WM8962_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
2677 #define WM8962_FLL_ENA_WIDTH 1 /* FLL_ENA */
2680 * R156 (0x9C) - FLL Control (2)
2682 #define WM8962_FLL_OUTDIV_MASK 0x01F8 /* FLL_OUTDIV - [8:3] */
2683 #define WM8962_FLL_OUTDIV_SHIFT 3 /* FLL_OUTDIV - [8:3] */
2684 #define WM8962_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [8:3] */
2685 #define WM8962_FLL_REFCLK_DIV_MASK 0x0003 /* FLL_REFCLK_DIV - [1:0] */
2686 #define WM8962_FLL_REFCLK_DIV_SHIFT 0 /* FLL_REFCLK_DIV - [1:0] */
2687 #define WM8962_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [1:0] */
2690 * R157 (0x9D) - FLL Control (3)
2692 #define WM8962_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
2693 #define WM8962_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
2694 #define WM8962_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
2697 * R159 (0x9F) - FLL Control (5)
2699 #define WM8962_FLL_FRC_NCO_VAL_MASK 0x007E /* FLL_FRC_NCO_VAL - [6:1] */
2700 #define WM8962_FLL_FRC_NCO_VAL_SHIFT 1 /* FLL_FRC_NCO_VAL - [6:1] */
2701 #define WM8962_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [6:1] */
2705 #define WM8962_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */
2708 * R160 (0xA0) - FLL Control (6)
2710 #define WM8962_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */
2711 #define WM8962_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */
2712 #define WM8962_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */
2715 * R161 (0xA1) - FLL Control (7)
2717 #define WM8962_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */
2718 #define WM8962_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */
2719 #define WM8962_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */
2722 * R162 (0xA2) - FLL Control (8)
2724 #define WM8962_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
2725 #define WM8962_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
2726 #define WM8962_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
2729 * R252 (0xFC) - General test 1
2734 #define WM8962_REG_SYNC_WIDTH 1 /* REG_SYNC */
2738 #define WM8962_AUTO_INC_WIDTH 1 /* AUTO_INC */
2741 * R256 (0x100) - DF1
2746 #define WM8962_DRC_DF1_ENA_WIDTH 1 /* DRC_DF1_ENA */
2750 #define WM8962_DF1_SHARED_COEFF_WIDTH 1 /* DF1_SHARED_COEFF */
2753 #define WM8962_DF1_SHARED_COEFF_SEL_SHIFT 1 /* DF1_SHARED_COEFF_SEL */
2754 #define WM8962_DF1_SHARED_COEFF_SEL_WIDTH 1 /* DF1_SHARED_COEFF_SEL */
2758 #define WM8962_DF1_ENA_WIDTH 1 /* DF1_ENA */
2761 * R257 (0x101) - DF2
2763 #define WM8962_DF1_COEFF_L0_MASK 0xFFFF /* DF1_COEFF_L0 - [15:0] */
2764 #define WM8962_DF1_COEFF_L0_SHIFT 0 /* DF1_COEFF_L0 - [15:0] */
2765 #define WM8962_DF1_COEFF_L0_WIDTH 16 /* DF1_COEFF_L0 - [15:0] */
2768 * R258 (0x102) - DF3
2770 #define WM8962_DF1_COEFF_L1_MASK 0xFFFF /* DF1_COEFF_L1 - [15:0] */
2771 #define WM8962_DF1_COEFF_L1_SHIFT 0 /* DF1_COEFF_L1 - [15:0] */
2772 #define WM8962_DF1_COEFF_L1_WIDTH 16 /* DF1_COEFF_L1 - [15:0] */
2775 * R259 (0x103) - DF4
2777 #define WM8962_DF1_COEFF_L2_MASK 0xFFFF /* DF1_COEFF_L2 - [15:0] */
2778 #define WM8962_DF1_COEFF_L2_SHIFT 0 /* DF1_COEFF_L2 - [15:0] */
2779 #define WM8962_DF1_COEFF_L2_WIDTH 16 /* DF1_COEFF_L2 - [15:0] */
2782 * R260 (0x104) - DF5
2784 #define WM8962_DF1_COEFF_R0_MASK 0xFFFF /* DF1_COEFF_R0 - [15:0] */
2785 #define WM8962_DF1_COEFF_R0_SHIFT 0 /* DF1_COEFF_R0 - [15:0] */
2786 #define WM8962_DF1_COEFF_R0_WIDTH 16 /* DF1_COEFF_R0 - [15:0] */
2789 * R261 (0x105) - DF6
2791 #define WM8962_DF1_COEFF_R1_MASK 0xFFFF /* DF1_COEFF_R1 - [15:0] */
2792 #define WM8962_DF1_COEFF_R1_SHIFT 0 /* DF1_COEFF_R1 - [15:0] */
2793 #define WM8962_DF1_COEFF_R1_WIDTH 16 /* DF1_COEFF_R1 - [15:0] */
2796 * R262 (0x106) - DF7
2798 #define WM8962_DF1_COEFF_R2_MASK 0xFFFF /* DF1_COEFF_R2 - [15:0] */
2799 #define WM8962_DF1_COEFF_R2_SHIFT 0 /* DF1_COEFF_R2 - [15:0] */
2800 #define WM8962_DF1_COEFF_R2_WIDTH 16 /* DF1_COEFF_R2 - [15:0] */
2803 * R264 (0x108) - LHPF1
2807 #define WM8962_LHPF_MODE_SHIFT 1 /* LHPF_MODE */
2808 #define WM8962_LHPF_MODE_WIDTH 1 /* LHPF_MODE */
2812 #define WM8962_LHPF_ENA_WIDTH 1 /* LHPF_ENA */
2815 * R265 (0x109) - LHPF2
2817 #define WM8962_LHPF_COEFF_MASK 0xFFFF /* LHPF_COEFF - [15:0] */
2818 #define WM8962_LHPF_COEFF_SHIFT 0 /* LHPF_COEFF - [15:0] */
2819 #define WM8962_LHPF_COEFF_WIDTH 16 /* LHPF_COEFF - [15:0] */
2822 * R268 (0x10C) - THREED1
2827 #define WM8962_ADC_MONOMIX_WIDTH 1 /* ADC_MONOMIX */
2831 #define WM8962_THREED_SIGN_L_WIDTH 1 /* THREED_SIGN_L */
2835 #define WM8962_THREED_SIGN_R_WIDTH 1 /* THREED_SIGN_R */
2839 #define WM8962_THREED_LHPF_MODE_WIDTH 1 /* THREED_LHPF_MODE */
2842 #define WM8962_THREED_LHPF_ENA_SHIFT 1 /* THREED_LHPF_ENA */
2843 #define WM8962_THREED_LHPF_ENA_WIDTH 1 /* THREED_LHPF_ENA */
2847 #define WM8962_THREED_ENA_WIDTH 1 /* THREED_ENA */
2850 * R269 (0x10D) - THREED2
2852 #define WM8962_THREED_FGAINL_MASK 0xF800 /* THREED_FGAINL - [15:11] */
2853 #define WM8962_THREED_FGAINL_SHIFT 11 /* THREED_FGAINL - [15:11] */
2854 #define WM8962_THREED_FGAINL_WIDTH 5 /* THREED_FGAINL - [15:11] */
2855 #define WM8962_THREED_CGAINL_MASK 0x07C0 /* THREED_CGAINL - [10:6] */
2856 #define WM8962_THREED_CGAINL_SHIFT 6 /* THREED_CGAINL - [10:6] */
2857 #define WM8962_THREED_CGAINL_WIDTH 5 /* THREED_CGAINL - [10:6] */
2858 #define WM8962_THREED_DELAYL_MASK 0x003C /* THREED_DELAYL - [5:2] */
2859 #define WM8962_THREED_DELAYL_SHIFT 2 /* THREED_DELAYL - [5:2] */
2860 #define WM8962_THREED_DELAYL_WIDTH 4 /* THREED_DELAYL - [5:2] */
2863 * R270 (0x10E) - THREED3
2865 #define WM8962_THREED_LHPF_COEFF_MASK 0xFFFF /* THREED_LHPF_COEFF - [15:0] */
2866 #define WM8962_THREED_LHPF_COEFF_SHIFT 0 /* THREED_LHPF_COEFF - [15:0] */
2867 #define WM8962_THREED_LHPF_COEFF_WIDTH 16 /* THREED_LHPF_COEFF - [15:0] */
2870 * R271 (0x10F) - THREED4
2872 #define WM8962_THREED_FGAINR_MASK 0xF800 /* THREED_FGAINR - [15:11] */
2873 #define WM8962_THREED_FGAINR_SHIFT 11 /* THREED_FGAINR - [15:11] */
2874 #define WM8962_THREED_FGAINR_WIDTH 5 /* THREED_FGAINR - [15:11] */
2875 #define WM8962_THREED_CGAINR_MASK 0x07C0 /* THREED_CGAINR - [10:6] */
2876 #define WM8962_THREED_CGAINR_SHIFT 6 /* THREED_CGAINR - [10:6] */
2877 #define WM8962_THREED_CGAINR_WIDTH 5 /* THREED_CGAINR - [10:6] */
2878 #define WM8962_THREED_DELAYR_MASK 0x003C /* THREED_DELAYR - [5:2] */
2879 #define WM8962_THREED_DELAYR_SHIFT 2 /* THREED_DELAYR - [5:2] */
2880 #define WM8962_THREED_DELAYR_WIDTH 4 /* THREED_DELAYR - [5:2] */
2883 * R276 (0x114) - DRC 1
2885 #define WM8962_DRC_SIG_DET_RMS_MASK 0x7C00 /* DRC_SIG_DET_RMS - [14:10] */
2886 #define WM8962_DRC_SIG_DET_RMS_SHIFT 10 /* DRC_SIG_DET_RMS - [14:10] */
2887 #define WM8962_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [14:10] */
2888 #define WM8962_DRC_SIG_DET_PK_MASK 0x0300 /* DRC_SIG_DET_PK - [9:8] */
2889 #define WM8962_DRC_SIG_DET_PK_SHIFT 8 /* DRC_SIG_DET_PK - [9:8] */
2890 #define WM8962_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [9:8] */
2894 #define WM8962_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */
2898 #define WM8962_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */
2902 #define WM8962_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */
2906 #define WM8962_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */
2910 #define WM8962_DRC_QR_WIDTH 1 /* DRC_QR */
2914 #define WM8962_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
2917 #define WM8962_DRC_MODE_SHIFT 1 /* DRC_MODE */
2918 #define WM8962_DRC_MODE_WIDTH 1 /* DRC_MODE */
2922 #define WM8962_DRC_ENA_WIDTH 1 /* DRC_ENA */
2925 * R277 (0x115) - DRC 2
2927 #define WM8962_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */
2928 #define WM8962_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */
2929 #define WM8962_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */
2930 #define WM8962_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */
2931 #define WM8962_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */
2932 #define WM8962_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */
2933 #define WM8962_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */
2934 #define WM8962_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */
2935 #define WM8962_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */
2936 #define WM8962_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
2937 #define WM8962_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
2938 #define WM8962_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
2941 * R278 (0x116) - DRC 3
2943 #define WM8962_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */
2944 #define WM8962_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */
2945 #define WM8962_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */
2946 #define WM8962_DRC_QR_THR_MASK 0x0C00 /* DRC_QR_THR - [11:10] */
2947 #define WM8962_DRC_QR_THR_SHIFT 10 /* DRC_QR_THR - [11:10] */
2948 #define WM8962_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [11:10] */
2949 #define WM8962_DRC_QR_DCY_MASK 0x0300 /* DRC_QR_DCY - [9:8] */
2950 #define WM8962_DRC_QR_DCY_SHIFT 8 /* DRC_QR_DCY - [9:8] */
2951 #define WM8962_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [9:8] */
2952 #define WM8962_DRC_NG_EXP_MASK 0x00C0 /* DRC_NG_EXP - [7:6] */
2953 #define WM8962_DRC_NG_EXP_SHIFT 6 /* DRC_NG_EXP - [7:6] */
2954 #define WM8962_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [7:6] */
2955 #define WM8962_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
2956 #define WM8962_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
2957 #define WM8962_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
2958 #define WM8962_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
2959 #define WM8962_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
2960 #define WM8962_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
2963 * R279 (0x117) - DRC 4
2965 #define WM8962_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
2966 #define WM8962_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
2967 #define WM8962_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
2968 #define WM8962_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
2969 #define WM8962_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
2970 #define WM8962_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
2973 * R280 (0x118) - DRC 5
2975 #define WM8962_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */
2976 #define WM8962_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */
2977 #define WM8962_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */
2978 #define WM8962_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */
2979 #define WM8962_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */
2980 #define WM8962_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */
2983 * R285 (0x11D) - Tloopback
2987 #define WM8962_TLB_ENA_SHIFT 1 /* TLB_ENA */
2988 #define WM8962_TLB_ENA_WIDTH 1 /* TLB_ENA */
2992 #define WM8962_TLB_MODE_WIDTH 1 /* TLB_MODE */
2995 * R335 (0x14F) - EQ1
3000 #define WM8962_EQ_SHARED_COEFF_WIDTH 1 /* EQ_SHARED_COEFF */
3003 #define WM8962_EQ_SHARED_COEFF_SEL_SHIFT 1 /* EQ_SHARED_COEFF_SEL */
3004 #define WM8962_EQ_SHARED_COEFF_SEL_WIDTH 1 /* EQ_SHARED_COEFF_SEL */
3008 #define WM8962_EQ_ENA_WIDTH 1 /* EQ_ENA */
3011 * R336 (0x150) - EQ2
3013 #define WM8962_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */
3014 #define WM8962_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */
3015 #define WM8962_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */
3016 #define WM8962_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */
3017 #define WM8962_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */
3018 #define WM8962_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */
3019 #define WM8962_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */
3020 #define WM8962_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */
3021 #define WM8962_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */
3024 * R337 (0x151) - EQ3
3026 #define WM8962_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */
3027 #define WM8962_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */
3028 #define WM8962_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */
3029 #define WM8962_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */
3030 #define WM8962_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */
3031 #define WM8962_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */
3034 * R338 (0x152) - EQ4
3036 #define WM8962_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */
3037 #define WM8962_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */
3038 #define WM8962_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */
3041 * R339 (0x153) - EQ5
3043 #define WM8962_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */
3044 #define WM8962_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */
3045 #define WM8962_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */
3048 * R340 (0x154) - EQ6
3050 #define WM8962_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */
3051 #define WM8962_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */
3052 #define WM8962_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */
3055 * R341 (0x155) - EQ7
3057 #define WM8962_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */
3058 #define WM8962_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */
3059 #define WM8962_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */
3062 * R342 (0x156) - EQ8
3064 #define WM8962_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */
3065 #define WM8962_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */
3066 #define WM8962_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */
3069 * R343 (0x157) - EQ9
3071 #define WM8962_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */
3072 #define WM8962_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */
3073 #define WM8962_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */
3076 * R344 (0x158) - EQ10
3078 #define WM8962_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */
3079 #define WM8962_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */
3080 #define WM8962_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */
3083 * R345 (0x159) - EQ11
3085 #define WM8962_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */
3086 #define WM8962_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */
3087 #define WM8962_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */
3090 * R346 (0x15A) - EQ12
3092 #define WM8962_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */
3093 #define WM8962_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */
3094 #define WM8962_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */
3097 * R347 (0x15B) - EQ13
3099 #define WM8962_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */
3100 #define WM8962_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */
3101 #define WM8962_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */
3104 * R348 (0x15C) - EQ14
3106 #define WM8962_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */
3107 #define WM8962_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */
3108 #define WM8962_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */
3111 * R349 (0x15D) - EQ15
3113 #define WM8962_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */
3114 #define WM8962_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */
3115 #define WM8962_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */
3118 * R350 (0x15E) - EQ16
3120 #define WM8962_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */
3121 #define WM8962_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */
3122 #define WM8962_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */
3125 * R351 (0x15F) - EQ17
3127 #define WM8962_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */
3128 #define WM8962_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */
3129 #define WM8962_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */
3132 * R352 (0x160) - EQ18
3134 #define WM8962_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */
3135 #define WM8962_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */
3136 #define WM8962_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */
3139 * R353 (0x161) - EQ19
3141 #define WM8962_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */
3142 #define WM8962_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */
3143 #define WM8962_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */
3146 * R354 (0x162) - EQ20
3148 #define WM8962_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */
3149 #define WM8962_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */
3150 #define WM8962_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */
3153 * R355 (0x163) - EQ21
3155 #define WM8962_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */
3156 #define WM8962_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */
3157 #define WM8962_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */
3160 * R356 (0x164) - EQ22
3162 #define WM8962_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */
3163 #define WM8962_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */
3164 #define WM8962_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */
3165 #define WM8962_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */
3166 #define WM8962_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */
3167 #define WM8962_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */
3168 #define WM8962_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */
3169 #define WM8962_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */
3170 #define WM8962_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */
3173 * R357 (0x165) - EQ23
3175 #define WM8962_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */
3176 #define WM8962_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */
3177 #define WM8962_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */
3178 #define WM8962_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */
3179 #define WM8962_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */
3180 #define WM8962_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */
3183 * R358 (0x166) - EQ24
3185 #define WM8962_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */
3186 #define WM8962_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */
3187 #define WM8962_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */
3190 * R359 (0x167) - EQ25
3192 #define WM8962_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */
3193 #define WM8962_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */
3194 #define WM8962_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */
3197 * R360 (0x168) - EQ26
3199 #define WM8962_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */
3200 #define WM8962_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */
3201 #define WM8962_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */
3204 * R361 (0x169) - EQ27
3206 #define WM8962_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */
3207 #define WM8962_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */
3208 #define WM8962_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */
3211 * R362 (0x16A) - EQ28
3213 #define WM8962_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */
3214 #define WM8962_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */
3215 #define WM8962_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */
3218 * R363 (0x16B) - EQ29
3220 #define WM8962_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */
3221 #define WM8962_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */
3222 #define WM8962_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */
3225 * R364 (0x16C) - EQ30
3227 #define WM8962_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */
3228 #define WM8962_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */
3229 #define WM8962_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */
3232 * R365 (0x16D) - EQ31
3234 #define WM8962_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */
3235 #define WM8962_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */
3236 #define WM8962_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */
3239 * R366 (0x16E) - EQ32
3241 #define WM8962_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */
3242 #define WM8962_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */
3243 #define WM8962_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */
3246 * R367 (0x16F) - EQ33
3248 #define WM8962_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */
3249 #define WM8962_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */
3250 #define WM8962_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */
3253 * R368 (0x170) - EQ34
3255 #define WM8962_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */
3256 #define WM8962_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */
3257 #define WM8962_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */
3260 * R369 (0x171) - EQ35
3262 #define WM8962_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */
3263 #define WM8962_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */
3264 #define WM8962_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */
3267 * R370 (0x172) - EQ36
3269 #define WM8962_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */
3270 #define WM8962_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */
3271 #define WM8962_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */
3274 * R371 (0x173) - EQ37
3276 #define WM8962_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */
3277 #define WM8962_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */
3278 #define WM8962_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */
3281 * R372 (0x174) - EQ38
3283 #define WM8962_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */
3284 #define WM8962_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */
3285 #define WM8962_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */
3288 * R373 (0x175) - EQ39
3290 #define WM8962_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */
3291 #define WM8962_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */
3292 #define WM8962_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */
3295 * R374 (0x176) - EQ40
3297 #define WM8962_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */
3298 #define WM8962_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */
3299 #define WM8962_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */
3302 * R375 (0x177) - EQ41
3304 #define WM8962_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */
3305 #define WM8962_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */
3306 #define WM8962_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */
3309 * R513 (0x201) - GPIO 2
3314 #define WM8962_GP2_POL_WIDTH 1 /* GP2_POL */
3318 #define WM8962_GP2_LVL_WIDTH 1 /* GP2_LVL */
3319 #define WM8962_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */
3320 #define WM8962_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */
3321 #define WM8962_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */
3324 * R514 (0x202) - GPIO 3
3329 #define WM8962_GP3_POL_WIDTH 1 /* GP3_POL */
3333 #define WM8962_GP3_LVL_WIDTH 1 /* GP3_LVL */
3334 #define WM8962_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */
3335 #define WM8962_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */
3336 #define WM8962_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */
3339 * R516 (0x204) - GPIO 5
3343 #define WM8962_GP5_DIR_SHIFT 15 /* GP5_DIR */
3344 #define WM8962_GP5_DIR_WIDTH 1 /* GP5_DIR */
3348 #define WM8962_GP5_PU_WIDTH 1 /* GP5_PU */
3352 #define WM8962_GP5_PD_WIDTH 1 /* GP5_PD */
3356 #define WM8962_GP5_POL_WIDTH 1 /* GP5_POL */
3360 #define WM8962_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3364 #define WM8962_GP5_DB_WIDTH 1 /* GP5_DB */
3368 #define WM8962_GP5_LVL_WIDTH 1 /* GP5_LVL */
3369 #define WM8962_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */
3370 #define WM8962_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */
3371 #define WM8962_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */
3374 * R517 (0x205) - GPIO 6
3378 #define WM8962_GP6_DIR_SHIFT 15 /* GP6_DIR */
3379 #define WM8962_GP6_DIR_WIDTH 1 /* GP6_DIR */
3383 #define WM8962_GP6_PU_WIDTH 1 /* GP6_PU */
3387 #define WM8962_GP6_PD_WIDTH 1 /* GP6_PD */
3391 #define WM8962_GP6_POL_WIDTH 1 /* GP6_POL */
3395 #define WM8962_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
3399 #define WM8962_GP6_DB_WIDTH 1 /* GP6_DB */
3403 #define WM8962_GP6_LVL_WIDTH 1 /* GP6_LVL */
3404 #define WM8962_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */
3405 #define WM8962_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */
3406 #define WM8962_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */
3409 * R560 (0x230) - Interrupt Status 1
3414 #define WM8962_GP6_EINT_WIDTH 1 /* GP6_EINT */
3418 #define WM8962_GP5_EINT_WIDTH 1 /* GP5_EINT */
3421 * R561 (0x231) - Interrupt Status 2
3425 #define WM8962_MICSCD_EINT_SHIFT 15 /* MICSCD_EINT */
3426 #define WM8962_MICSCD_EINT_WIDTH 1 /* MICSCD_EINT */
3430 #define WM8962_MICD_EINT_WIDTH 1 /* MICD_EINT */
3434 #define WM8962_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3438 #define WM8962_ALC_LOCK_EINT_WIDTH 1 /* ALC_LOCK_EINT */
3442 #define WM8962_ALC_THRESH_EINT_WIDTH 1 /* ALC_THRESH_EINT */
3446 #define WM8962_ALC_SAT_EINT_WIDTH 1 /* ALC_SAT_EINT */
3450 #define WM8962_ALC_PKOVR_EINT_WIDTH 1 /* ALC_PKOVR_EINT */
3454 #define WM8962_ALC_NGATE_EINT_WIDTH 1 /* ALC_NGATE_EINT */
3458 #define WM8962_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3462 #define WM8962_DRC_ACTDET_EINT_WIDTH 1 /* DRC_ACTDET_EINT */
3466 #define WM8962_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */
3470 #define WM8962_PLL3_LOCK_EINT_WIDTH 1 /* PLL3_LOCK_EINT */
3474 #define WM8962_PLL2_LOCK_EINT_WIDTH 1 /* PLL2_LOCK_EINT */
3478 #define WM8962_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */
3481 * R568 (0x238) - Interrupt Status 1 Mask
3486 #define WM8962_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
3490 #define WM8962_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
3493 * R569 (0x239) - Interrupt Status 2 Mask
3497 #define WM8962_IM_MICSCD_EINT_SHIFT 15 /* IM_MICSCD_EINT */
3498 #define WM8962_IM_MICSCD_EINT_WIDTH 1 /* IM_MICSCD_EINT */
3502 #define WM8962_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
3506 #define WM8962_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
3510 #define WM8962_IM_ALC_LOCK_EINT_WIDTH 1 /* IM_ALC_LOCK_EINT */
3514 #define WM8962_IM_ALC_THRESH_EINT_WIDTH 1 /* IM_ALC_THRESH_EINT */
3518 #define WM8962_IM_ALC_SAT_EINT_WIDTH 1 /* IM_ALC_SAT_EINT */
3522 #define WM8962_IM_ALC_PKOVR_EINT_WIDTH 1 /* IM_ALC_PKOVR_EINT */
3526 #define WM8962_IM_ALC_NGATE_EINT_WIDTH 1 /* IM_ALC_NGATE_EINT */
3530 #define WM8962_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
3534 #define WM8962_IM_DRC_ACTDET_EINT_WIDTH 1 /* IM_DRC_ACTDET_EINT */
3538 #define WM8962_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */
3542 #define WM8962_IM_PLL3_LOCK_EINT_WIDTH 1 /* IM_PLL3_LOCK_EINT */
3546 #define WM8962_IM_PLL2_LOCK_EINT_WIDTH 1 /* IM_PLL2_LOCK_EINT */
3550 #define WM8962_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */
3553 * R576 (0x240) - Interrupt Control
3558 #define WM8962_IRQ_POL_WIDTH 1 /* IRQ_POL */
3561 * R584 (0x248) - IRQ Debounce
3566 #define WM8962_FLL_LOCK_DB_WIDTH 1 /* FLL_LOCK_DB */
3570 #define WM8962_PLL3_LOCK_DB_WIDTH 1 /* PLL3_LOCK_DB */
3574 #define WM8962_PLL2_LOCK_DB_WIDTH 1 /* PLL2_LOCK_DB */
3578 #define WM8962_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */
3581 * R586 (0x24A) - MICINT Source Pol
3585 #define WM8962_MICSCD_IRQ_POL_SHIFT 15 /* MICSCD_IRQ_POL */
3586 #define WM8962_MICSCD_IRQ_POL_WIDTH 1 /* MICSCD_IRQ_POL */
3590 #define WM8962_MICD_IRQ_POL_WIDTH 1 /* MICD_IRQ_POL */
3593 * R768 (0x300) - DSP2 Power Management
3598 #define WM8962_DSP2_ENA_WIDTH 1 /* DSP2_ENA */
3601 * R1037 (0x40D) - DSP2_ExecControl
3606 #define WM8962_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */
3610 #define WM8962_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */
3614 #define WM8962_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */
3618 #define WM8962_DSP2_STOP_WIDTH 1 /* DSP2_STOP */
3621 #define WM8962_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */
3622 #define WM8962_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */
3626 #define WM8962_DSP2_RUN_WIDTH 1 /* DSP2_RUN */
3629 * R8192 (0x2000) - DSP2 Instruction RAM 0
3631 #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_MASK 0x03FF /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */
3632 #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_SHIFT 0 /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */
3633 #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_WIDTH 10 /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */
3636 * R9216 (0x2400) - DSP2 Address RAM 2
3638 #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_MASK 0x003F /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */
3639 #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */
3640 #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_WIDTH 6 /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */
3643 * R9217 (0x2401) - DSP2 Address RAM 1
3645 #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_MASK 0xFFFF /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */
3646 #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */
3647 #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_WIDTH 16 /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */
3650 * R9218 (0x2402) - DSP2 Address RAM 0
3652 #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_MASK 0xFFFF /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */
3653 #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */
3654 #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_WIDTH 16 /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */
3657 * R12288 (0x3000) - DSP2 Data1 RAM 1
3659 #define WM8962_DSP2_DATA1_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */
3660 #define WM8962_DSP2_DATA1_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */
3661 #define WM8962_DSP2_DATA1_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */
3664 * R12289 (0x3001) - DSP2 Data1 RAM 0
3666 #define WM8962_DSP2_DATA1_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */
3667 #define WM8962_DSP2_DATA1_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */
3668 #define WM8962_DSP2_DATA1_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */
3671 * R13312 (0x3400) - DSP2 Data2 RAM 1
3673 #define WM8962_DSP2_DATA2_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */
3674 #define WM8962_DSP2_DATA2_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */
3675 #define WM8962_DSP2_DATA2_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */
3678 * R13313 (0x3401) - DSP2 Data2 RAM 0
3680 #define WM8962_DSP2_DATA2_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */
3681 #define WM8962_DSP2_DATA2_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */
3682 #define WM8962_DSP2_DATA2_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */
3685 * R14336 (0x3800) - DSP2 Data3 RAM 1
3687 #define WM8962_DSP2_DATA3_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */
3688 #define WM8962_DSP2_DATA3_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */
3689 #define WM8962_DSP2_DATA3_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */
3692 * R14337 (0x3801) - DSP2 Data3 RAM 0
3694 #define WM8962_DSP2_DATA3_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */
3695 #define WM8962_DSP2_DATA3_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */
3696 #define WM8962_DSP2_DATA3_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */
3699 * R15360 (0x3C00) - DSP2 Coeff RAM 0
3701 #define WM8962_DSP2_CMAP_RAM_384_11_10_0_MASK 0x07FF /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */
3702 #define WM8962_DSP2_CMAP_RAM_384_11_10_0_SHIFT 0 /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */
3703 #define WM8962_DSP2_CMAP_RAM_384_11_10_0_WIDTH 11 /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */
3706 * R16384 (0x4000) - RETUNEADC_SHARED_COEFF_1
3711 #define WM8962_ADC_RETUNE_SCV_WIDTH 1 /* ADC_RETUNE_SCV */
3712 #define WM8962_RETUNEADC_SHARED_COEFF_22_16_MASK 0x007F /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */
3713 #define WM8962_RETUNEADC_SHARED_COEFF_22_16_SHIFT 0 /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */
3714 #define WM8962_RETUNEADC_SHARED_COEFF_22_16_WIDTH 7 /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */
3717 * R16385 (0x4001) - RETUNEADC_SHARED_COEFF_0
3719 #define WM8962_RETUNEADC_SHARED_COEFF_15_00_MASK 0xFFFF /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */
3720 #define WM8962_RETUNEADC_SHARED_COEFF_15_00_SHIFT 0 /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] …
3721 #define WM8962_RETUNEADC_SHARED_COEFF_15_00_WIDTH 16 /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] …
3724 * R16386 (0x4002) - RETUNEDAC_SHARED_COEFF_1
3729 #define WM8962_DAC_RETUNE_SCV_WIDTH 1 /* DAC_RETUNE_SCV */
3730 #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_MASK 0x007F /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */
3731 #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_SHIFT 0 /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */
3732 #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_WIDTH 7 /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */
3735 * R16387 (0x4003) - RETUNEDAC_SHARED_COEFF_0
3737 #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_MASK 0xFFFF /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */
3738 #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_SHIFT 0 /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] …
3739 #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_WIDTH 16 /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] …
3742 * R16388 (0x4004) - SOUNDSTAGE_ENABLES_1
3744 #define WM8962_SOUNDSTAGE_ENABLES_23_16_MASK 0x00FF /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */
3745 #define WM8962_SOUNDSTAGE_ENABLES_23_16_SHIFT 0 /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */
3746 #define WM8962_SOUNDSTAGE_ENABLES_23_16_WIDTH 8 /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */
3749 * R16389 (0x4005) - SOUNDSTAGE_ENABLES_0
3751 #define WM8962_SOUNDSTAGE_ENABLES_15_06_MASK 0xFFC0 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */
3752 #define WM8962_SOUNDSTAGE_ENABLES_15_06_SHIFT 6 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */
3753 #define WM8962_SOUNDSTAGE_ENABLES_15_06_WIDTH 10 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */
3757 #define WM8962_RTN_ADC_ENA_WIDTH 1 /* RTN_ADC_ENA */
3761 #define WM8962_RTN_DAC_ENA_WIDTH 1 /* RTN_DAC_ENA */
3765 #define WM8962_HDBASS_ENA_WIDTH 1 /* HDBASS_ENA */
3769 #define WM8962_HPF2_ENA_WIDTH 1 /* HPF2_ENA */
3772 #define WM8962_HPF1_ENA_SHIFT 1 /* HPF1_ENA */
3773 #define WM8962_HPF1_ENA_WIDTH 1 /* HPF1_ENA */
3777 #define WM8962_VSS_ENA_WIDTH 1 /* VSS_ENA */