Lines Matching +full:asoc +full:- +full:wm8904
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm8904.h -- WM8904 ASoC driver
137 * R0 (0x00) - SW Reset and ID
139 #define WM8904_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
140 #define WM8904_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
141 #define WM8904_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
144 * R1 (0x01) - Revision
146 #define WM8904_REVISION_MASK 0x000F /* REVISION - [3:0] */
147 #define WM8904_REVISION_SHIFT 0 /* REVISION - [3:0] */
148 #define WM8904_REVISION_WIDTH 16 /* REVISION - [3:0] */
151 * R4 (0x04) - Bias Control 0
157 #define WM8904_ISEL_MASK 0x000C /* ISEL - [3:2] */
158 #define WM8904_ISEL_SHIFT 2 /* ISEL - [3:2] */
159 #define WM8904_ISEL_WIDTH 2 /* ISEL - [3:2] */
170 * R5 (0x05) - VMID Control 0
176 #define WM8904_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */
177 #define WM8904_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */
178 #define WM8904_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */
185 * R8 (0x08) - Analogue DAC 0
187 #define WM8904_DAC_BIAS_SEL_MASK 0x0018 /* DAC_BIAS_SEL - [4:3] */
188 #define WM8904_DAC_BIAS_SEL_SHIFT 3 /* DAC_BIAS_SEL - [4:3] */
189 #define WM8904_DAC_BIAS_SEL_WIDTH 2 /* DAC_BIAS_SEL - [4:3] */
190 #define WM8904_DAC_VMID_BIAS_SEL_MASK 0x0006 /* DAC_VMID_BIAS_SEL - [2:1] */
191 #define WM8904_DAC_VMID_BIAS_SEL_SHIFT 1 /* DAC_VMID_BIAS_SEL - [2:1] */
192 #define WM8904_DAC_VMID_BIAS_SEL_WIDTH 2 /* DAC_VMID_BIAS_SEL - [2:1] */
195 * R9 (0x09) - mic Filter Control
197 #define WM8904_MIC_DET_SET_THRESHOLD_MASK 0xF000 /* MIC_DET_SET_THRESHOLD - [15:12] */
198 #define WM8904_MIC_DET_SET_THRESHOLD_SHIFT 12 /* MIC_DET_SET_THRESHOLD - [15:12] */
199 #define WM8904_MIC_DET_SET_THRESHOLD_WIDTH 4 /* MIC_DET_SET_THRESHOLD - [15:12] */
200 #define WM8904_MIC_DET_RESET_THRESHOLD_MASK 0x0F00 /* MIC_DET_RESET_THRESHOLD - [11:8] */
201 #define WM8904_MIC_DET_RESET_THRESHOLD_SHIFT 8 /* MIC_DET_RESET_THRESHOLD - [11:8] */
202 #define WM8904_MIC_DET_RESET_THRESHOLD_WIDTH 4 /* MIC_DET_RESET_THRESHOLD - [11:8] */
203 #define WM8904_MIC_SHORT_SET_THRESHOLD_MASK 0x00F0 /* MIC_SHORT_SET_THRESHOLD - [7:4] */
204 #define WM8904_MIC_SHORT_SET_THRESHOLD_SHIFT 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */
205 #define WM8904_MIC_SHORT_SET_THRESHOLD_WIDTH 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */
206 #define WM8904_MIC_SHORT_RESET_THRESHOLD_MASK 0x000F /* MIC_SHORT_RESET_THRESHOLD - [3:0] */
207 #define WM8904_MIC_SHORT_RESET_THRESHOLD_SHIFT 0 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */
208 #define WM8904_MIC_SHORT_RESET_THRESHOLD_WIDTH 4 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */
211 * R10 (0x0A) - Analogue ADC 0
219 * R12 (0x0C) - Power Management 0
231 * R14 (0x0E) - Power Management 2
243 * R15 (0x0F) - Power Management 3
255 * R18 (0x12) - Power Management 6
275 * R20 (0x14) - Clock Rates 0
295 * R21 (0x15) - Clock Rates 1
297 #define WM8904_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */
298 #define WM8904_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */
299 #define WM8904_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */
300 #define WM8904_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */
301 #define WM8904_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */
302 #define WM8904_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */
305 * R22 (0x16) - Clock Rates 2
337 * R24 (0x18) - Audio Interface 0
347 #define WM8904_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */
348 #define WM8904_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */
349 #define WM8904_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */
388 * R25 (0x19) - Audio Interface 1
422 #define WM8904_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
423 #define WM8904_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
424 #define WM8904_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
425 #define WM8904_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
426 #define WM8904_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
427 #define WM8904_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
430 * R26 (0x1A) - Audio Interface 2
432 #define WM8904_OPCLK_DIV_MASK 0x0F00 /* OPCLK_DIV - [11:8] */
433 #define WM8904_OPCLK_DIV_SHIFT 8 /* OPCLK_DIV - [11:8] */
434 #define WM8904_OPCLK_DIV_WIDTH 4 /* OPCLK_DIV - [11:8] */
435 #define WM8904_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
436 #define WM8904_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
437 #define WM8904_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
440 * R27 (0x1B) - Audio Interface 3
446 #define WM8904_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
447 #define WM8904_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
448 #define WM8904_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
451 * R30 (0x1E) - DAC Digital Volume Left
457 #define WM8904_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
458 #define WM8904_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
459 #define WM8904_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
462 * R31 (0x1F) - DAC Digital Volume Right
468 #define WM8904_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
469 #define WM8904_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
470 #define WM8904_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
473 * R32 (0x20) - DAC Digital 0
475 #define WM8904_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */
476 #define WM8904_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */
477 #define WM8904_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */
478 #define WM8904_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */
479 #define WM8904_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */
480 #define WM8904_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */
481 #define WM8904_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
482 #define WM8904_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
483 #define WM8904_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
484 #define WM8904_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */
485 #define WM8904_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */
486 #define WM8904_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */
489 * R33 (0x21) - DAC Digital 1
515 #define WM8904_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
516 #define WM8904_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
517 #define WM8904_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
520 * R36 (0x24) - ADC Digital Volume Left
526 #define WM8904_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
527 #define WM8904_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
528 #define WM8904_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
531 * R37 (0x25) - ADC Digital Volume Right
537 #define WM8904_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
538 #define WM8904_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
539 #define WM8904_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
542 * R38 (0x26) - ADC Digital 0
544 #define WM8904_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */
545 #define WM8904_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */
546 #define WM8904_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */
561 * R39 (0x27) - Digital Microphone 0
573 * R40 (0x28) - DRC 0
583 #define WM8904_DRC_GS_HYST_LVL_MASK 0x1800 /* DRC_GS_HYST_LVL - [12:11] */
584 #define WM8904_DRC_GS_HYST_LVL_SHIFT 11 /* DRC_GS_HYST_LVL - [12:11] */
585 #define WM8904_DRC_GS_HYST_LVL_WIDTH 2 /* DRC_GS_HYST_LVL - [12:11] */
586 #define WM8904_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
587 #define WM8904_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
588 #define WM8904_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
611 * R41 (0x29) - DRC 1
613 #define WM8904_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
614 #define WM8904_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
615 #define WM8904_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
616 #define WM8904_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
617 #define WM8904_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
618 #define WM8904_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
619 #define WM8904_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
620 #define WM8904_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
621 #define WM8904_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
622 #define WM8904_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
623 #define WM8904_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
624 #define WM8904_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
625 #define WM8904_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
626 #define WM8904_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
627 #define WM8904_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
628 #define WM8904_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
629 #define WM8904_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
630 #define WM8904_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
633 * R42 (0x2A) - DRC 2
635 #define WM8904_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
636 #define WM8904_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
637 #define WM8904_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
638 #define WM8904_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
639 #define WM8904_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
640 #define WM8904_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
643 * R43 (0x2B) - DRC 3
645 #define WM8904_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
646 #define WM8904_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
647 #define WM8904_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
648 #define WM8904_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
649 #define WM8904_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
650 #define WM8904_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
653 * R44 (0x2C) - Analogue Left Input 0
659 #define WM8904_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */
660 #define WM8904_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */
661 #define WM8904_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */
664 * R45 (0x2D) - Analogue Right Input 0
670 #define WM8904_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */
671 #define WM8904_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */
672 #define WM8904_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */
675 * R46 (0x2E) - Analogue Left Input 1
681 #define WM8904_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */
682 #define WM8904_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */
683 #define WM8904_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */
684 #define WM8904_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */
685 #define WM8904_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */
686 #define WM8904_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */
687 #define WM8904_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */
688 #define WM8904_L_MODE_SHIFT 0 /* L_MODE - [1:0] */
689 #define WM8904_L_MODE_WIDTH 2 /* L_MODE - [1:0] */
692 * R47 (0x2F) - Analogue Right Input 1
698 #define WM8904_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */
699 #define WM8904_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */
700 #define WM8904_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */
701 #define WM8904_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */
702 #define WM8904_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */
703 #define WM8904_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */
704 #define WM8904_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */
705 #define WM8904_R_MODE_SHIFT 0 /* R_MODE - [1:0] */
706 #define WM8904_R_MODE_WIDTH 2 /* R_MODE - [1:0] */
709 * R57 (0x39) - Analogue OUT1 Left
723 #define WM8904_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */
724 #define WM8904_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */
725 #define WM8904_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */
728 * R58 (0x3A) - Analogue OUT1 Right
742 #define WM8904_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */
743 #define WM8904_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */
744 #define WM8904_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */
747 * R59 (0x3B) - Analogue OUT2 Left
761 #define WM8904_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */
762 #define WM8904_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */
763 #define WM8904_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */
766 * R60 (0x3C) - Analogue OUT2 Right
780 #define WM8904_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */
781 #define WM8904_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */
782 #define WM8904_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */
785 * R61 (0x3D) - Analogue OUT12 ZC
805 * R67 (0x43) - DC Servo 0
825 * R68 (0x44) - DC Servo 1
893 * R69 (0x45) - DC Servo 2
895 #define WM8904_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
896 #define WM8904_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
897 #define WM8904_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
898 #define WM8904_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
899 #define WM8904_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
900 #define WM8904_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
903 * R71 (0x47) - DC Servo 4
905 #define WM8904_DCS_SERIES_NO_23_MASK 0x007F /* DCS_SERIES_NO_23 - [6:0] */
906 #define WM8904_DCS_SERIES_NO_23_SHIFT 0 /* DCS_SERIES_NO_23 - [6:0] */
907 #define WM8904_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [6:0] */
910 * R72 (0x48) - DC Servo 5
912 #define WM8904_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
913 #define WM8904_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
914 #define WM8904_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
917 * R73 (0x49) - DC Servo 6
919 #define WM8904_DCS_DAC_WR_VAL_3_MASK 0x00FF /* DCS_DAC_WR_VAL_3 - [7:0] */
920 #define WM8904_DCS_DAC_WR_VAL_3_SHIFT 0 /* DCS_DAC_WR_VAL_3 - [7:0] */
921 #define WM8904_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [7:0] */
924 * R74 (0x4A) - DC Servo 7
926 #define WM8904_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
927 #define WM8904_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
928 #define WM8904_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
931 * R75 (0x4B) - DC Servo 8
933 #define WM8904_DCS_DAC_WR_VAL_1_MASK 0x00FF /* DCS_DAC_WR_VAL_1 - [7:0] */
934 #define WM8904_DCS_DAC_WR_VAL_1_SHIFT 0 /* DCS_DAC_WR_VAL_1 - [7:0] */
935 #define WM8904_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [7:0] */
938 * R76 (0x4C) - DC Servo 9
940 #define WM8904_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
941 #define WM8904_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
942 #define WM8904_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
945 * R77 (0x4D) - DC Servo Readback 0
947 #define WM8904_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
948 #define WM8904_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
949 #define WM8904_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
950 #define WM8904_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
951 #define WM8904_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
952 #define WM8904_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
953 #define WM8904_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
954 #define WM8904_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
955 #define WM8904_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
958 * R90 (0x5A) - Analogue HP 0
994 * R94 (0x5E) - Analogue Lineout 0
1030 * R98 (0x62) - Charge Pump 0
1038 * R104 (0x68) - Class W 0
1046 * R108 (0x6C) - Write Sequencer 0
1052 #define WM8904_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */
1053 #define WM8904_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */
1054 #define WM8904_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */
1057 * R109 (0x6D) - Write Sequencer 1
1059 #define WM8904_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */
1060 #define WM8904_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */
1061 #define WM8904_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */
1062 #define WM8904_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */
1063 #define WM8904_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */
1064 #define WM8904_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */
1065 #define WM8904_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
1066 #define WM8904_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
1067 #define WM8904_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
1070 * R110 (0x6E) - Write Sequencer 2
1076 #define WM8904_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */
1077 #define WM8904_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */
1078 #define WM8904_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */
1079 #define WM8904_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
1080 #define WM8904_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
1081 #define WM8904_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
1084 * R111 (0x6F) - Write Sequencer 3
1094 #define WM8904_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
1095 #define WM8904_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
1096 #define WM8904_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
1099 * R112 (0x70) - Write Sequencer 4
1101 #define WM8904_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */
1102 #define WM8904_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */
1103 #define WM8904_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */
1110 * R116 (0x74) - FLL Control 1
1126 * R117 (0x75) - FLL Control 2
1128 #define WM8904_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
1129 #define WM8904_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
1130 #define WM8904_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
1131 #define WM8904_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
1132 #define WM8904_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
1133 #define WM8904_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
1134 #define WM8904_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
1135 #define WM8904_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
1136 #define WM8904_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
1139 * R118 (0x76) - FLL Control 3
1141 #define WM8904_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
1142 #define WM8904_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
1143 #define WM8904_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
1146 * R119 (0x77) - FLL Control 4
1148 #define WM8904_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
1149 #define WM8904_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
1150 #define WM8904_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
1151 #define WM8904_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
1152 #define WM8904_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
1153 #define WM8904_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
1156 * R120 (0x78) - FLL Control 5
1158 #define WM8904_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
1159 #define WM8904_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
1160 #define WM8904_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
1161 #define WM8904_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */
1162 #define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
1163 #define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
1166 * R126 (0x7E) - Digital Pulls
1202 * R127 (0x7F) - Interrupt Status
1250 * R128 (0x80) - Interrupt Status Mask
1294 * R129 (0x81) - Interrupt Polarity
1338 * R130 (0x82) - Interrupt Debounce
1382 * R134 (0x86) - EQ1
1390 * R135 (0x87) - EQ2
1392 #define WM8904_EQ_B1_GAIN_MASK 0x001F /* EQ_B1_GAIN - [4:0] */
1393 #define WM8904_EQ_B1_GAIN_SHIFT 0 /* EQ_B1_GAIN - [4:0] */
1394 #define WM8904_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [4:0] */
1397 * R136 (0x88) - EQ3
1399 #define WM8904_EQ_B2_GAIN_MASK 0x001F /* EQ_B2_GAIN - [4:0] */
1400 #define WM8904_EQ_B2_GAIN_SHIFT 0 /* EQ_B2_GAIN - [4:0] */
1401 #define WM8904_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [4:0] */
1404 * R137 (0x89) - EQ4
1406 #define WM8904_EQ_B3_GAIN_MASK 0x001F /* EQ_B3_GAIN - [4:0] */
1407 #define WM8904_EQ_B3_GAIN_SHIFT 0 /* EQ_B3_GAIN - [4:0] */
1408 #define WM8904_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [4:0] */
1411 * R138 (0x8A) - EQ5
1413 #define WM8904_EQ_B4_GAIN_MASK 0x001F /* EQ_B4_GAIN - [4:0] */
1414 #define WM8904_EQ_B4_GAIN_SHIFT 0 /* EQ_B4_GAIN - [4:0] */
1415 #define WM8904_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [4:0] */
1418 * R139 (0x8B) - EQ6
1420 #define WM8904_EQ_B5_GAIN_MASK 0x001F /* EQ_B5_GAIN - [4:0] */
1421 #define WM8904_EQ_B5_GAIN_SHIFT 0 /* EQ_B5_GAIN - [4:0] */
1422 #define WM8904_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [4:0] */
1425 * R140 (0x8C) - EQ7
1427 #define WM8904_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
1428 #define WM8904_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
1429 #define WM8904_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
1432 * R141 (0x8D) - EQ8
1434 #define WM8904_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
1435 #define WM8904_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
1436 #define WM8904_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
1439 * R142 (0x8E) - EQ9
1441 #define WM8904_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
1442 #define WM8904_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
1443 #define WM8904_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
1446 * R143 (0x8F) - EQ10
1448 #define WM8904_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
1449 #define WM8904_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
1450 #define WM8904_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
1453 * R144 (0x90) - EQ11
1455 #define WM8904_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
1456 #define WM8904_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
1457 #define WM8904_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
1460 * R145 (0x91) - EQ12
1462 #define WM8904_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
1463 #define WM8904_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
1464 #define WM8904_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
1467 * R146 (0x92) - EQ13
1469 #define WM8904_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
1470 #define WM8904_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
1471 #define WM8904_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
1474 * R147 (0x93) - EQ14
1476 #define WM8904_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
1477 #define WM8904_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
1478 #define WM8904_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
1481 * R148 (0x94) - EQ15
1483 #define WM8904_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
1484 #define WM8904_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
1485 #define WM8904_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
1488 * R149 (0x95) - EQ16
1490 #define WM8904_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
1491 #define WM8904_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
1492 #define WM8904_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
1495 * R150 (0x96) - EQ17
1497 #define WM8904_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
1498 #define WM8904_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
1499 #define WM8904_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
1502 * R151 (0x97) - EQ18
1504 #define WM8904_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
1505 #define WM8904_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
1506 #define WM8904_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
1509 * R152 (0x98) - EQ19
1511 #define WM8904_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
1512 #define WM8904_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
1513 #define WM8904_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
1516 * R153 (0x99) - EQ20
1518 #define WM8904_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
1519 #define WM8904_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
1520 #define WM8904_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
1523 * R154 (0x9A) - EQ21
1525 #define WM8904_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
1526 #define WM8904_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
1527 #define WM8904_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
1530 * R155 (0x9B) - EQ22
1532 #define WM8904_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
1533 #define WM8904_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
1534 #define WM8904_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
1537 * R156 (0x9C) - EQ23
1539 #define WM8904_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
1540 #define WM8904_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
1541 #define WM8904_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
1544 * R157 (0x9D) - EQ24
1546 #define WM8904_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
1547 #define WM8904_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
1548 #define WM8904_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
1551 * R161 (0xA1) - Control Interface Test 1
1559 * R198 (0xC6) - ADC Test 0
1569 * R204 (0xCC) - Analogue Output Bias 0
1571 #define WM8904_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */
1572 #define WM8904_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */
1573 #define WM8904_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */
1576 * R247 (0xF7) - FLL NCO Test 0
1584 * R248 (0xF8) - FLL NCO Test 1
1586 #define WM8904_FLL_FRC_NCO_VAL_MASK 0x003F /* FLL_FRC_NCO_VAL - [5:0] */
1587 #define WM8904_FLL_FRC_NCO_VAL_SHIFT 0 /* FLL_FRC_NCO_VAL - [5:0] */
1588 #define WM8904_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [5:0] */