soc/codecs/wm8903.c

68 	{ 40, 0x09BF },     /* R40  - DRC 0 */
69 	{ 41, 0x3241 },     /* R41  - DRC 1 */
70 	{ 42, 0x0020 },     /* R42  - DRC 2 */
71 	{ 43, 0x0000 },     /* R43  - DRC 3 */
667 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
668 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
669 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
670 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
672 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
673 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
674 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
675 SOC_ENUM("DRC Attack Rate", drc_attack),
676 SOC_ENUM("DRC Decay Rate", drc_decay),
677 SOC_ENUM("DRC FF Delay", drc_ff_delay),
678 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
679 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
680 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
681 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
682 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
683 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
684 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
685 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),