Lines Matching +full:1 +full:- +full:15

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * wm5100.h  --  WM5100 ALSA SoC Audio driver
18 #define WM5100_CLK_AIF1     1
27 #define WM5100_CLKSRC_MCLK2    1
36 #define WM5100_FLL1 1
891  * R0 (0x00) - software reset
893 #define WM5100_SW_RST_DEV_ID1_MASK              0xFFFF  /* SW_RST_DEV_ID1 - [15:0] */
894 #define WM5100_SW_RST_DEV_ID1_SHIFT                  0  /* SW_RST_DEV_ID1 - [15:0] */
895 #define WM5100_SW_RST_DEV_ID1_WIDTH                 16  /* SW_RST_DEV_ID1 - [15:0] */
898  * R1 (0x01) - Device Revision
900 #define WM5100_DEVICE_REVISION_MASK             0x000F  /* DEVICE_REVISION - [3:0] */
901 #define WM5100_DEVICE_REVISION_SHIFT                 0  /* DEVICE_REVISION - [3:0] */
902 #define WM5100_DEVICE_REVISION_WIDTH                 4  /* DEVICE_REVISION - [3:0] */
905  * R16 (0x10) - Ctrl IF 1
910 #define WM5100_AUTO_INC_WIDTH                        1  /* AUTO_INC */
913  * R32 (0x20) - Tone Generator 1
915 #define WM5100_TONE_RATE_MASK                   0x3000  /* TONE_RATE - [13:12] */
916 #define WM5100_TONE_RATE_SHIFT                      12  /* TONE_RATE - [13:12] */
917 #define WM5100_TONE_RATE_WIDTH                       2  /* TONE_RATE - [13:12] */
918 #define WM5100_TONE_OFFSET_MASK                 0x0300  /* TONE_OFFSET - [9:8] */
919 #define WM5100_TONE_OFFSET_SHIFT                     8  /* TONE_OFFSET - [9:8] */
920 #define WM5100_TONE_OFFSET_WIDTH                     2  /* TONE_OFFSET - [9:8] */
923 #define WM5100_TONE2_ENA_SHIFT                       1  /* TONE2_ENA */
924 #define WM5100_TONE2_ENA_WIDTH                       1  /* TONE2_ENA */
928 #define WM5100_TONE1_ENA_WIDTH                       1  /* TONE1_ENA */
931  * R48 (0x30) - PWM Drive 1
933 #define WM5100_PWM_RATE_MASK                    0x3000  /* PWM_RATE - [13:12] */
934 #define WM5100_PWM_RATE_SHIFT                       12  /* PWM_RATE - [13:12] */
935 #define WM5100_PWM_RATE_WIDTH                        2  /* PWM_RATE - [13:12] */
936 #define WM5100_PWM_CLK_SEL_MASK                 0x0300  /* PWM_CLK_SEL - [9:8] */
937 #define WM5100_PWM_CLK_SEL_SHIFT                     8  /* PWM_CLK_SEL - [9:8] */
938 #define WM5100_PWM_CLK_SEL_WIDTH                     2  /* PWM_CLK_SEL - [9:8] */
942 #define WM5100_PWM2_OVD_WIDTH                        1  /* PWM2_OVD */
946 #define WM5100_PWM1_OVD_WIDTH                        1  /* PWM1_OVD */
949 #define WM5100_PWM2_ENA_SHIFT                        1  /* PWM2_ENA */
950 #define WM5100_PWM2_ENA_WIDTH                        1  /* PWM2_ENA */
954 #define WM5100_PWM1_ENA_WIDTH                        1  /* PWM1_ENA */
957  * R49 (0x31) - PWM Drive 2
959 #define WM5100_PWM1_LVL_MASK                    0x03FF  /* PWM1_LVL - [9:0] */
960 #define WM5100_PWM1_LVL_SHIFT                        0  /* PWM1_LVL - [9:0] */
961 #define WM5100_PWM1_LVL_WIDTH                       10  /* PWM1_LVL - [9:0] */
964  * R50 (0x32) - PWM Drive 3
966 #define WM5100_PWM2_LVL_MASK                    0x03FF  /* PWM2_LVL - [9:0] */
967 #define WM5100_PWM2_LVL_SHIFT                        0  /* PWM2_LVL - [9:0] */
968 #define WM5100_PWM2_LVL_WIDTH                       10  /* PWM2_LVL - [9:0] */
971  * R256 (0x100) - Clocking 1
973 #define WM5100_CLK_32K_SRC_MASK                 0x000F  /* CLK_32K_SRC - [3:0] */
974 #define WM5100_CLK_32K_SRC_SHIFT                     0  /* CLK_32K_SRC - [3:0] */
975 #define WM5100_CLK_32K_SRC_WIDTH                     4  /* CLK_32K_SRC - [3:0] */
978  * R257 (0x101) - Clocking 3
980 #define WM5100_SYSCLK_FREQ_MASK                 0x0700  /* SYSCLK_FREQ - [10:8] */
981 #define WM5100_SYSCLK_FREQ_SHIFT                     8  /* SYSCLK_FREQ - [10:8] */
982 #define WM5100_SYSCLK_FREQ_WIDTH                     3  /* SYSCLK_FREQ - [10:8] */
986 #define WM5100_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
987 #define WM5100_SYSCLK_SRC_MASK                  0x000F  /* SYSCLK_SRC - [3:0] */
988 #define WM5100_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC - [3:0] */
989 #define WM5100_SYSCLK_SRC_WIDTH                      4  /* SYSCLK_SRC - [3:0] */
992  * R258 (0x102) - Clocking 4
994 #define WM5100_SAMPLE_RATE_1_MASK               0x001F  /* SAMPLE_RATE_1 - [4:0] */
995 #define WM5100_SAMPLE_RATE_1_SHIFT                   0  /* SAMPLE_RATE_1 - [4:0] */
996 #define WM5100_SAMPLE_RATE_1_WIDTH                   5  /* SAMPLE_RATE_1 - [4:0] */
999  * R259 (0x103) - Clocking 5
1001 #define WM5100_SAMPLE_RATE_2_MASK               0x001F  /* SAMPLE_RATE_2 - [4:0] */
1002 #define WM5100_SAMPLE_RATE_2_SHIFT                   0  /* SAMPLE_RATE_2 - [4:0] */
1003 #define WM5100_SAMPLE_RATE_2_WIDTH                   5  /* SAMPLE_RATE_2 - [4:0] */
1006  * R260 (0x104) - Clocking 6
1008 #define WM5100_SAMPLE_RATE_3_MASK               0x001F  /* SAMPLE_RATE_3 - [4:0] */
1009 #define WM5100_SAMPLE_RATE_3_SHIFT                   0  /* SAMPLE_RATE_3 - [4:0] */
1010 #define WM5100_SAMPLE_RATE_3_WIDTH                   5  /* SAMPLE_RATE_3 - [4:0] */
1013  * R263 (0x107) - Clocking 7
1015 #define WM5100_ASYNC_CLK_FREQ_MASK              0x0700  /* ASYNC_CLK_FREQ - [10:8] */
1016 #define WM5100_ASYNC_CLK_FREQ_SHIFT                  8  /* ASYNC_CLK_FREQ - [10:8] */
1017 #define WM5100_ASYNC_CLK_FREQ_WIDTH                  3  /* ASYNC_CLK_FREQ - [10:8] */
1021 #define WM5100_ASYNC_CLK_ENA_WIDTH                   1  /* ASYNC_CLK_ENA */
1022 #define WM5100_ASYNC_CLK_SRC_MASK               0x000F  /* ASYNC_CLK_SRC - [3:0] */
1023 #define WM5100_ASYNC_CLK_SRC_SHIFT                   0  /* ASYNC_CLK_SRC - [3:0] */
1024 #define WM5100_ASYNC_CLK_SRC_WIDTH                   4  /* ASYNC_CLK_SRC - [3:0] */
1027  * R264 (0x108) - Clocking 8
1029 #define WM5100_ASYNC_SAMPLE_RATE_MASK           0x001F  /* ASYNC_SAMPLE_RATE - [4:0] */
1030 #define WM5100_ASYNC_SAMPLE_RATE_SHIFT               0  /* ASYNC_SAMPLE_RATE - [4:0] */
1031 #define WM5100_ASYNC_SAMPLE_RATE_WIDTH               5  /* ASYNC_SAMPLE_RATE - [4:0] */
1034  * R288 (0x120) - ASRC_ENABLE
1039 #define WM5100_ASRC2L_ENA_WIDTH                      1  /* ASRC2L_ENA */
1043 #define WM5100_ASRC2R_ENA_WIDTH                      1  /* ASRC2R_ENA */
1046 #define WM5100_ASRC1L_ENA_SHIFT                      1  /* ASRC1L_ENA */
1047 #define WM5100_ASRC1L_ENA_WIDTH                      1  /* ASRC1L_ENA */
1051 #define WM5100_ASRC1R_ENA_WIDTH                      1  /* ASRC1R_ENA */
1054  * R289 (0x121) - ASRC_STATUS
1059 #define WM5100_ASRC2L_ENA_STS_WIDTH                  1  /* ASRC2L_ENA_STS */
1063 #define WM5100_ASRC2R_ENA_STS_WIDTH                  1  /* ASRC2R_ENA_STS */
1066 #define WM5100_ASRC1L_ENA_STS_SHIFT                  1  /* ASRC1L_ENA_STS */
1067 #define WM5100_ASRC1L_ENA_STS_WIDTH                  1  /* ASRC1L_ENA_STS */
1071 #define WM5100_ASRC1R_ENA_STS_WIDTH                  1  /* ASRC1R_ENA_STS */
1074  * R290 (0x122) - ASRC_RATE1
1076 #define WM5100_ASRC_RATE1_MASK                  0x0006  /* ASRC_RATE1 - [2:1] */
1077 #define WM5100_ASRC_RATE1_SHIFT                      1  /* ASRC_RATE1 - [2:1] */
1078 #define WM5100_ASRC_RATE1_WIDTH                      2  /* ASRC_RATE1 - [2:1] */
1081  * R321 (0x141) - ISRC 1 CTRL 1
1086 #define WM5100_ISRC1_DFS_ENA_WIDTH                   1  /* ISRC1_DFS_ENA */
1087 #define WM5100_ISRC1_CLK_SEL_MASK               0x0300  /* ISRC1_CLK_SEL - [9:8] */
1088 #define WM5100_ISRC1_CLK_SEL_SHIFT                   8  /* ISRC1_CLK_SEL - [9:8] */
1089 #define WM5100_ISRC1_CLK_SEL_WIDTH                   2  /* ISRC1_CLK_SEL - [9:8] */
1090 #define WM5100_ISRC1_FSH_MASK                   0x000C  /* ISRC1_FSH - [3:2] */
1091 #define WM5100_ISRC1_FSH_SHIFT                       2  /* ISRC1_FSH - [3:2] */
1092 #define WM5100_ISRC1_FSH_WIDTH                       2  /* ISRC1_FSH - [3:2] */
1093 #define WM5100_ISRC1_FSL_MASK                   0x0003  /* ISRC1_FSL - [1:0] */
1094 #define WM5100_ISRC1_FSL_SHIFT                       0  /* ISRC1_FSL - [1:0] */
1095 #define WM5100_ISRC1_FSL_WIDTH                       2  /* ISRC1_FSL - [1:0] */
1098  * R322 (0x142) - ISRC 1 CTRL 2
1102 #define WM5100_ISRC1_INT1_ENA_SHIFT                 15  /* ISRC1_INT1_ENA */
1103 #define WM5100_ISRC1_INT1_ENA_WIDTH                  1  /* ISRC1_INT1_ENA */
1107 #define WM5100_ISRC1_INT2_ENA_WIDTH                  1  /* ISRC1_INT2_ENA */
1111 #define WM5100_ISRC1_INT3_ENA_WIDTH                  1  /* ISRC1_INT3_ENA */
1115 #define WM5100_ISRC1_INT4_ENA_WIDTH                  1  /* ISRC1_INT4_ENA */
1119 #define WM5100_ISRC1_DEC1_ENA_WIDTH                  1  /* ISRC1_DEC1_ENA */
1123 #define WM5100_ISRC1_DEC2_ENA_WIDTH                  1  /* ISRC1_DEC2_ENA */
1127 #define WM5100_ISRC1_DEC3_ENA_WIDTH                  1  /* ISRC1_DEC3_ENA */
1131 #define WM5100_ISRC1_DEC4_ENA_WIDTH                  1  /* ISRC1_DEC4_ENA */
1135 #define WM5100_ISRC1_NOTCH_ENA_WIDTH                 1  /* ISRC1_NOTCH_ENA */
1138  * R323 (0x143) - ISRC 2 CTRL1
1143 #define WM5100_ISRC2_DFS_ENA_WIDTH                   1  /* ISRC2_DFS_ENA */
1144 #define WM5100_ISRC2_CLK_SEL_MASK               0x0300  /* ISRC2_CLK_SEL - [9:8] */
1145 #define WM5100_ISRC2_CLK_SEL_SHIFT                   8  /* ISRC2_CLK_SEL - [9:8] */
1146 #define WM5100_ISRC2_CLK_SEL_WIDTH                   2  /* ISRC2_CLK_SEL - [9:8] */
1147 #define WM5100_ISRC2_FSH_MASK                   0x000C  /* ISRC2_FSH - [3:2] */
1148 #define WM5100_ISRC2_FSH_SHIFT                       2  /* ISRC2_FSH - [3:2] */
1149 #define WM5100_ISRC2_FSH_WIDTH                       2  /* ISRC2_FSH - [3:2] */
1150 #define WM5100_ISRC2_FSL_MASK                   0x0003  /* ISRC2_FSL - [1:0] */
1151 #define WM5100_ISRC2_FSL_SHIFT                       0  /* ISRC2_FSL - [1:0] */
1152 #define WM5100_ISRC2_FSL_WIDTH                       2  /* ISRC2_FSL - [1:0] */
1155  * R324 (0x144) - ISRC 2 CTRL 2
1159 #define WM5100_ISRC2_INT1_ENA_SHIFT                 15  /* ISRC2_INT1_ENA */
1160 #define WM5100_ISRC2_INT1_ENA_WIDTH                  1  /* ISRC2_INT1_ENA */
1164 #define WM5100_ISRC2_INT2_ENA_WIDTH                  1  /* ISRC2_INT2_ENA */
1168 #define WM5100_ISRC2_INT3_ENA_WIDTH                  1  /* ISRC2_INT3_ENA */
1172 #define WM5100_ISRC2_INT4_ENA_WIDTH                  1  /* ISRC2_INT4_ENA */
1176 #define WM5100_ISRC2_DEC1_ENA_WIDTH                  1  /* ISRC2_DEC1_ENA */
1180 #define WM5100_ISRC2_DEC2_ENA_WIDTH                  1  /* ISRC2_DEC2_ENA */
1184 #define WM5100_ISRC2_DEC3_ENA_WIDTH                  1  /* ISRC2_DEC3_ENA */
1188 #define WM5100_ISRC2_DEC4_ENA_WIDTH                  1  /* ISRC2_DEC4_ENA */
1192 #define WM5100_ISRC2_NOTCH_ENA_WIDTH                 1  /* ISRC2_NOTCH_ENA */
1195  * R386 (0x182) - FLL1 Control 1
1200 #define WM5100_FLL1_ENA_WIDTH                        1  /* FLL1_ENA */
1203  * R387 (0x183) - FLL1 Control 2
1205 #define WM5100_FLL1_OUTDIV_MASK                 0x3F00  /* FLL1_OUTDIV - [13:8] */
1206 #define WM5100_FLL1_OUTDIV_SHIFT                     8  /* FLL1_OUTDIV - [13:8] */
1207 #define WM5100_FLL1_OUTDIV_WIDTH                     6  /* FLL1_OUTDIV - [13:8] */
1208 #define WM5100_FLL1_FRATIO_MASK                 0x0007  /* FLL1_FRATIO - [2:0] */
1209 #define WM5100_FLL1_FRATIO_SHIFT                     0  /* FLL1_FRATIO - [2:0] */
1210 #define WM5100_FLL1_FRATIO_WIDTH                     3  /* FLL1_FRATIO - [2:0] */
1213  * R388 (0x184) - FLL1 Control 3
1215 #define WM5100_FLL1_THETA_MASK                  0xFFFF  /* FLL1_THETA - [15:0] */
1216 #define WM5100_FLL1_THETA_SHIFT                      0  /* FLL1_THETA - [15:0] */
1217 #define WM5100_FLL1_THETA_WIDTH                     16  /* FLL1_THETA - [15:0] */
1220  * R390 (0x186) - FLL1 Control 5
1222 #define WM5100_FLL1_N_MASK                      0x03FF  /* FLL1_N - [9:0] */
1223 #define WM5100_FLL1_N_SHIFT                          0  /* FLL1_N - [9:0] */
1224 #define WM5100_FLL1_N_WIDTH                         10  /* FLL1_N - [9:0] */
1227  * R391 (0x187) - FLL1 Control 6
1229 #define WM5100_FLL1_REFCLK_DIV_MASK             0x00C0  /* FLL1_REFCLK_DIV - [7:6] */
1230 #define WM5100_FLL1_REFCLK_DIV_SHIFT                 6  /* FLL1_REFCLK_DIV - [7:6] */
1231 #define WM5100_FLL1_REFCLK_DIV_WIDTH                 2  /* FLL1_REFCLK_DIV - [7:6] */
1232 #define WM5100_FLL1_REFCLK_SRC_MASK             0x000F  /* FLL1_REFCLK_SRC - [3:0] */
1233 #define WM5100_FLL1_REFCLK_SRC_SHIFT                 0  /* FLL1_REFCLK_SRC - [3:0] */
1234 #define WM5100_FLL1_REFCLK_SRC_WIDTH                 4  /* FLL1_REFCLK_SRC - [3:0] */
1237  * R392 (0x188) - FLL1 EFS 1
1239 #define WM5100_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
1240 #define WM5100_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
1241 #define WM5100_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
1244  * R418 (0x1A2) - FLL2 Control 1
1249 #define WM5100_FLL2_ENA_WIDTH                        1  /* FLL2_ENA */
1252  * R419 (0x1A3) - FLL2 Control 2
1254 #define WM5100_FLL2_OUTDIV_MASK                 0x3F00  /* FLL2_OUTDIV - [13:8] */
1255 #define WM5100_FLL2_OUTDIV_SHIFT                     8  /* FLL2_OUTDIV - [13:8] */
1256 #define WM5100_FLL2_OUTDIV_WIDTH                     6  /* FLL2_OUTDIV - [13:8] */
1257 #define WM5100_FLL2_FRATIO_MASK                 0x0007  /* FLL2_FRATIO - [2:0] */
1258 #define WM5100_FLL2_FRATIO_SHIFT                     0  /* FLL2_FRATIO - [2:0] */
1259 #define WM5100_FLL2_FRATIO_WIDTH                     3  /* FLL2_FRATIO - [2:0] */
1262  * R420 (0x1A4) - FLL2 Control 3
1264 #define WM5100_FLL2_THETA_MASK                  0xFFFF  /* FLL2_THETA - [15:0] */
1265 #define WM5100_FLL2_THETA_SHIFT                      0  /* FLL2_THETA - [15:0] */
1266 #define WM5100_FLL2_THETA_WIDTH                     16  /* FLL2_THETA - [15:0] */
1269  * R422 (0x1A6) - FLL2 Control 5
1271 #define WM5100_FLL2_N_MASK                      0x03FF  /* FLL2_N - [9:0] */
1272 #define WM5100_FLL2_N_SHIFT                          0  /* FLL2_N - [9:0] */
1273 #define WM5100_FLL2_N_WIDTH                         10  /* FLL2_N - [9:0] */
1276  * R423 (0x1A7) - FLL2 Control 6
1278 #define WM5100_FLL2_REFCLK_DIV_MASK             0x00C0  /* FLL2_REFCLK_DIV - [7:6] */
1279 #define WM5100_FLL2_REFCLK_DIV_SHIFT                 6  /* FLL2_REFCLK_DIV - [7:6] */
1280 #define WM5100_FLL2_REFCLK_DIV_WIDTH                 2  /* FLL2_REFCLK_DIV - [7:6] */
1281 #define WM5100_FLL2_REFCLK_SRC_MASK             0x000F  /* FLL2_REFCLK_SRC - [3:0] */
1282 #define WM5100_FLL2_REFCLK_SRC_SHIFT                 0  /* FLL2_REFCLK_SRC - [3:0] */
1283 #define WM5100_FLL2_REFCLK_SRC_WIDTH                 4  /* FLL2_REFCLK_SRC - [3:0] */
1286  * R424 (0x1A8) - FLL2 EFS 1
1288 #define WM5100_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
1289 #define WM5100_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
1290 #define WM5100_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
1293  * R512 (0x200) - Mic Charge Pump 1
1298 #define WM5100_CP2_BYPASS_WIDTH                      1  /* CP2_BYPASS */
1302 #define WM5100_CP2_ENA_WIDTH                         1  /* CP2_ENA */
1305  * R513 (0x201) - Mic Charge Pump 2
1307 #define WM5100_LDO2_VSEL_MASK                   0xF800  /* LDO2_VSEL - [15:11] */
1308 #define WM5100_LDO2_VSEL_SHIFT                      11  /* LDO2_VSEL - [15:11] */
1309 #define WM5100_LDO2_VSEL_WIDTH                       5  /* LDO2_VSEL - [15:11] */
1312  * R514 (0x202) - HP Charge Pump 1
1317 #define WM5100_CP1_ENA_WIDTH                         1  /* CP1_ENA */
1320  * R529 (0x211) - LDO1 Control
1324 #define WM5100_LDO1_BYPASS_SHIFT                     1  /* LDO1_BYPASS */
1325 #define WM5100_LDO1_BYPASS_WIDTH                     1  /* LDO1_BYPASS */
1328  * R533 (0x215) - Mic Bias Ctrl 1
1333 #define WM5100_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
1337 #define WM5100_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
1338 #define WM5100_MICB1_LVL_MASK                   0x001C  /* MICB1_LVL - [4:2] */
1339 #define WM5100_MICB1_LVL_SHIFT                       2  /* MICB1_LVL - [4:2] */
1340 #define WM5100_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [4:2] */
1343 #define WM5100_MICB1_BYPASS_SHIFT                    1  /* MICB1_BYPASS */
1344 #define WM5100_MICB1_BYPASS_WIDTH                    1  /* MICB1_BYPASS */
1348 #define WM5100_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
1351  * R534 (0x216) - Mic Bias Ctrl 2
1356 #define WM5100_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
1360 #define WM5100_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
1361 #define WM5100_MICB2_LVL_MASK                   0x001C  /* MICB2_LVL - [4:2] */
1362 #define WM5100_MICB2_LVL_SHIFT                       2  /* MICB2_LVL - [4:2] */
1363 #define WM5100_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [4:2] */
1366 #define WM5100_MICB2_BYPASS_SHIFT                    1  /* MICB2_BYPASS */
1367 #define WM5100_MICB2_BYPASS_WIDTH                    1  /* MICB2_BYPASS */
1371 #define WM5100_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
1374  * R535 (0x217) - Mic Bias Ctrl 3
1379 #define WM5100_MICB3_DISCH_WIDTH                     1  /* MICB3_DISCH */
1383 #define WM5100_MICB3_RATE_WIDTH                      1  /* MICB3_RATE */
1384 #define WM5100_MICB3_LVL_MASK                   0x001C  /* MICB3_LVL - [4:2] */
1385 #define WM5100_MICB3_LVL_SHIFT                       2  /* MICB3_LVL - [4:2] */
1386 #define WM5100_MICB3_LVL_WIDTH                       3  /* MICB3_LVL - [4:2] */
1389 #define WM5100_MICB3_BYPASS_SHIFT                    1  /* MICB3_BYPASS */
1390 #define WM5100_MICB3_BYPASS_WIDTH                    1  /* MICB3_BYPASS */
1394 #define WM5100_MICB3_ENA_WIDTH                       1  /* MICB3_ENA */
1397  * R640 (0x280) - Accessory Detect Mode 1
1399 #define WM5100_ACCDET_BIAS_SRC_MASK             0xC000  /* ACCDET_BIAS_SRC - [15:14] */
1400 #define WM5100_ACCDET_BIAS_SRC_SHIFT                14  /* ACCDET_BIAS_SRC - [15:14] */
1401 #define WM5100_ACCDET_BIAS_SRC_WIDTH                 2  /* ACCDET_BIAS_SRC - [15:14] */
1405 #define WM5100_ACCDET_SRC_WIDTH                      1  /* ACCDET_SRC */
1406 #define WM5100_ACCDET_MODE_MASK                 0x0003  /* ACCDET_MODE - [1:0] */
1407 #define WM5100_ACCDET_MODE_SHIFT                     0  /* ACCDET_MODE - [1:0] */
1408 #define WM5100_ACCDET_MODE_WIDTH                     2  /* ACCDET_MODE - [1:0] */
1411  * R648 (0x288) - Headphone Detect 1
1413 #define WM5100_HP_HOLDTIME_MASK                 0x00E0  /* HP_HOLDTIME - [7:5] */
1414 #define WM5100_HP_HOLDTIME_SHIFT                     5  /* HP_HOLDTIME - [7:5] */
1415 #define WM5100_HP_HOLDTIME_WIDTH                     3  /* HP_HOLDTIME - [7:5] */
1416 #define WM5100_HP_CLK_DIV_MASK                  0x0018  /* HP_CLK_DIV - [4:3] */
1417 #define WM5100_HP_CLK_DIV_SHIFT                      3  /* HP_CLK_DIV - [4:3] */
1418 #define WM5100_HP_CLK_DIV_WIDTH                      2  /* HP_CLK_DIV - [4:3] */
1421 #define WM5100_HP_STEP_SIZE_SHIFT                    1  /* HP_STEP_SIZE */
1422 #define WM5100_HP_STEP_SIZE_WIDTH                    1  /* HP_STEP_SIZE */
1426 #define WM5100_HP_POLL_WIDTH                         1  /* HP_POLL */
1429  * R649 (0x289) - Headphone Detect 2
1434 #define WM5100_HP_DONE_WIDTH                         1  /* HP_DONE */
1435 #define WM5100_HP_LVL_MASK                      0x007F  /* HP_LVL - [6:0] */
1436 #define WM5100_HP_LVL_SHIFT                          0  /* HP_LVL - [6:0] */
1437 #define WM5100_HP_LVL_WIDTH                          7  /* HP_LVL - [6:0] */
1440  * R656 (0x290) - Mic Detect 1
1442 #define WM5100_ACCDET_BIAS_STARTTIME_MASK       0xF000  /* ACCDET_BIAS_STARTTIME - [15:12] */
1443 #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT          12  /* ACCDET_BIAS_STARTTIME - [15:12] */
1444 #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH           4  /* ACCDET_BIAS_STARTTIME - [15:12] */
1445 #define WM5100_ACCDET_RATE_MASK                 0x0F00  /* ACCDET_RATE - [11:8] */
1446 #define WM5100_ACCDET_RATE_SHIFT                     8  /* ACCDET_RATE - [11:8] */
1447 #define WM5100_ACCDET_RATE_WIDTH                     4  /* ACCDET_RATE - [11:8] */
1450 #define WM5100_ACCDET_DBTIME_SHIFT                   1  /* ACCDET_DBTIME */
1451 #define WM5100_ACCDET_DBTIME_WIDTH                   1  /* ACCDET_DBTIME */
1455 #define WM5100_ACCDET_ENA_WIDTH                      1  /* ACCDET_ENA */
1458  * R657 (0x291) - Mic Detect 2
1460 #define WM5100_ACCDET_LVL_SEL_MASK              0x00FF  /* ACCDET_LVL_SEL - [7:0] */
1461 #define WM5100_ACCDET_LVL_SEL_SHIFT                  0  /* ACCDET_LVL_SEL - [7:0] */
1462 #define WM5100_ACCDET_LVL_SEL_WIDTH                  8  /* ACCDET_LVL_SEL - [7:0] */
1465  * R658 (0x292) - Mic Detect 3
1467 #define WM5100_ACCDET_LVL_MASK                  0x07FC  /* ACCDET_LVL - [10:2] */
1468 #define WM5100_ACCDET_LVL_SHIFT                      2  /* ACCDET_LVL - [10:2] */
1469 #define WM5100_ACCDET_LVL_WIDTH                      9  /* ACCDET_LVL - [10:2] */
1472 #define WM5100_ACCDET_VALID_SHIFT                    1  /* ACCDET_VALID */
1473 #define WM5100_ACCDET_VALID_WIDTH                    1  /* ACCDET_VALID */
1477 #define WM5100_ACCDET_STS_WIDTH                      1  /* ACCDET_STS */
1480  * R699 (0x2BB) - Misc Control
1486  * R769 (0x301) - Input Enables
1491 #define WM5100_IN4L_ENA_WIDTH                        1  /* IN4L_ENA */
1495 #define WM5100_IN4R_ENA_WIDTH                        1  /* IN4R_ENA */
1499 #define WM5100_IN3L_ENA_WIDTH                        1  /* IN3L_ENA */
1503 #define WM5100_IN3R_ENA_WIDTH                        1  /* IN3R_ENA */
1507 #define WM5100_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
1511 #define WM5100_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
1514 #define WM5100_IN1L_ENA_SHIFT                        1  /* IN1L_ENA */
1515 #define WM5100_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
1519 #define WM5100_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
1522  * R770 (0x302) - Input Enables Status
1527 #define WM5100_IN4L_ENA_STS_WIDTH                    1  /* IN4L_ENA_STS */
1531 #define WM5100_IN4R_ENA_STS_WIDTH                    1  /* IN4R_ENA_STS */
1535 #define WM5100_IN3L_ENA_STS_WIDTH                    1  /* IN3L_ENA_STS */
1539 #define WM5100_IN3R_ENA_STS_WIDTH                    1  /* IN3R_ENA_STS */
1543 #define WM5100_IN2L_ENA_STS_WIDTH                    1  /* IN2L_ENA_STS */
1547 #define WM5100_IN2R_ENA_STS_WIDTH                    1  /* IN2R_ENA_STS */
1550 #define WM5100_IN1L_ENA_STS_SHIFT                    1  /* IN1L_ENA_STS */
1551 #define WM5100_IN1L_ENA_STS_WIDTH                    1  /* IN1L_ENA_STS */
1555 #define WM5100_IN1R_ENA_STS_WIDTH                    1  /* IN1R_ENA_STS */
1558  * R784 (0x310) - IN1L Control
1560 #define WM5100_IN_RATE_MASK                     0xC000  /* IN_RATE - [15:14] */
1561 #define WM5100_IN_RATE_SHIFT                        14  /* IN_RATE - [15:14] */
1562 #define WM5100_IN_RATE_WIDTH                         2  /* IN_RATE - [15:14] */
1566 #define WM5100_IN1_OSR_WIDTH                         1  /* IN1_OSR */
1567 #define WM5100_IN1_DMIC_SUP_MASK                0x1800  /* IN1_DMIC_SUP - [12:11] */
1568 #define WM5100_IN1_DMIC_SUP_SHIFT                   11  /* IN1_DMIC_SUP - [12:11] */
1569 #define WM5100_IN1_DMIC_SUP_WIDTH                    2  /* IN1_DMIC_SUP - [12:11] */
1570 #define WM5100_IN1_MODE_MASK                    0x0600  /* IN1_MODE - [10:9] */
1571 #define WM5100_IN1_MODE_SHIFT                        9  /* IN1_MODE - [10:9] */
1572 #define WM5100_IN1_MODE_WIDTH                        2  /* IN1_MODE - [10:9] */
1573 #define WM5100_IN1L_PGA_VOL_MASK                0x00FE  /* IN1L_PGA_VOL - [7:1] */
1574 #define WM5100_IN1L_PGA_VOL_SHIFT                    1  /* IN1L_PGA_VOL - [7:1] */
1575 #define WM5100_IN1L_PGA_VOL_WIDTH                    7  /* IN1L_PGA_VOL - [7:1] */
1578  * R785 (0x311) - IN1R Control
1580 #define WM5100_IN1R_PGA_VOL_MASK                0x00FE  /* IN1R_PGA_VOL - [7:1] */
1581 #define WM5100_IN1R_PGA_VOL_SHIFT                    1  /* IN1R_PGA_VOL - [7:1] */
1582 #define WM5100_IN1R_PGA_VOL_WIDTH                    7  /* IN1R_PGA_VOL - [7:1] */
1585  * R786 (0x312) - IN2L Control
1590 #define WM5100_IN2_OSR_WIDTH                         1  /* IN2_OSR */
1591 #define WM5100_IN2_DMIC_SUP_MASK                0x1800  /* IN2_DMIC_SUP - [12:11] */
1592 #define WM5100_IN2_DMIC_SUP_SHIFT                   11  /* IN2_DMIC_SUP - [12:11] */
1593 #define WM5100_IN2_DMIC_SUP_WIDTH                    2  /* IN2_DMIC_SUP - [12:11] */
1594 #define WM5100_IN2_MODE_MASK                    0x0600  /* IN2_MODE - [10:9] */
1595 #define WM5100_IN2_MODE_SHIFT                        9  /* IN2_MODE - [10:9] */
1596 #define WM5100_IN2_MODE_WIDTH                        2  /* IN2_MODE - [10:9] */
1597 #define WM5100_IN2L_PGA_VOL_MASK                0x00FE  /* IN2L_PGA_VOL - [7:1] */
1598 #define WM5100_IN2L_PGA_VOL_SHIFT                    1  /* IN2L_PGA_VOL - [7:1] */
1599 #define WM5100_IN2L_PGA_VOL_WIDTH                    7  /* IN2L_PGA_VOL - [7:1] */
1602  * R787 (0x313) - IN2R Control
1604 #define WM5100_IN2R_PGA_VOL_MASK                0x00FE  /* IN2R_PGA_VOL - [7:1] */
1605 #define WM5100_IN2R_PGA_VOL_SHIFT                    1  /* IN2R_PGA_VOL - [7:1] */
1606 #define WM5100_IN2R_PGA_VOL_WIDTH                    7  /* IN2R_PGA_VOL - [7:1] */
1609  * R788 (0x314) - IN3L Control
1614 #define WM5100_IN3_OSR_WIDTH                         1  /* IN3_OSR */
1615 #define WM5100_IN3_DMIC_SUP_MASK                0x1800  /* IN3_DMIC_SUP - [12:11] */
1616 #define WM5100_IN3_DMIC_SUP_SHIFT                   11  /* IN3_DMIC_SUP - [12:11] */
1617 #define WM5100_IN3_DMIC_SUP_WIDTH                    2  /* IN3_DMIC_SUP - [12:11] */
1618 #define WM5100_IN3_MODE_MASK                    0x0600  /* IN3_MODE - [10:9] */
1619 #define WM5100_IN3_MODE_SHIFT                        9  /* IN3_MODE - [10:9] */
1620 #define WM5100_IN3_MODE_WIDTH                        2  /* IN3_MODE - [10:9] */
1621 #define WM5100_IN3L_PGA_VOL_MASK                0x00FE  /* IN3L_PGA_VOL - [7:1] */
1622 #define WM5100_IN3L_PGA_VOL_SHIFT                    1  /* IN3L_PGA_VOL - [7:1] */
1623 #define WM5100_IN3L_PGA_VOL_WIDTH                    7  /* IN3L_PGA_VOL - [7:1] */
1626  * R789 (0x315) - IN3R Control
1628 #define WM5100_IN3R_PGA_VOL_MASK                0x00FE  /* IN3R_PGA_VOL - [7:1] */
1629 #define WM5100_IN3R_PGA_VOL_SHIFT                    1  /* IN3R_PGA_VOL - [7:1] */
1630 #define WM5100_IN3R_PGA_VOL_WIDTH                    7  /* IN3R_PGA_VOL - [7:1] */
1633  * R790 (0x316) - IN4L Control
1638 #define WM5100_IN4_OSR_WIDTH                         1  /* IN4_OSR */
1639 #define WM5100_IN4_DMIC_SUP_MASK                0x1800  /* IN4_DMIC_SUP - [12:11] */
1640 #define WM5100_IN4_DMIC_SUP_SHIFT                   11  /* IN4_DMIC_SUP - [12:11] */
1641 #define WM5100_IN4_DMIC_SUP_WIDTH                    2  /* IN4_DMIC_SUP - [12:11] */
1642 #define WM5100_IN4_MODE_MASK                    0x0600  /* IN4_MODE - [10:9] */
1643 #define WM5100_IN4_MODE_SHIFT                        9  /* IN4_MODE - [10:9] */
1644 #define WM5100_IN4_MODE_WIDTH                        2  /* IN4_MODE - [10:9] */
1645 #define WM5100_IN4L_PGA_VOL_MASK                0x00FE  /* IN4L_PGA_VOL - [7:1] */
1646 #define WM5100_IN4L_PGA_VOL_SHIFT                    1  /* IN4L_PGA_VOL - [7:1] */
1647 #define WM5100_IN4L_PGA_VOL_WIDTH                    7  /* IN4L_PGA_VOL - [7:1] */
1650  * R791 (0x317) - IN4R Control
1652 #define WM5100_IN4R_PGA_VOL_MASK                0x00FE  /* IN4R_PGA_VOL - [7:1] */
1653 #define WM5100_IN4R_PGA_VOL_SHIFT                    1  /* IN4R_PGA_VOL - [7:1] */
1654 #define WM5100_IN4R_PGA_VOL_WIDTH                    7  /* IN4R_PGA_VOL - [7:1] */
1657  * R792 (0x318) - RXANC_SRC
1659 #define WM5100_IN_RXANC_SEL_MASK                0x0007  /* IN_RXANC_SEL - [2:0] */
1660 #define WM5100_IN_RXANC_SEL_SHIFT                    0  /* IN_RXANC_SEL - [2:0] */
1661 #define WM5100_IN_RXANC_SEL_WIDTH                    3  /* IN_RXANC_SEL - [2:0] */
1664  * R793 (0x319) - Input Volume Ramp
1666 #define WM5100_IN_VD_RAMP_MASK                  0x0070  /* IN_VD_RAMP - [6:4] */
1667 #define WM5100_IN_VD_RAMP_SHIFT                      4  /* IN_VD_RAMP - [6:4] */
1668 #define WM5100_IN_VD_RAMP_WIDTH                      3  /* IN_VD_RAMP - [6:4] */
1669 #define WM5100_IN_VI_RAMP_MASK                  0x0007  /* IN_VI_RAMP - [2:0] */
1670 #define WM5100_IN_VI_RAMP_SHIFT                      0  /* IN_VI_RAMP - [2:0] */
1671 #define WM5100_IN_VI_RAMP_WIDTH                      3  /* IN_VI_RAMP - [2:0] */
1674  * R800 (0x320) - ADC Digital Volume 1L
1679 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1683 #define WM5100_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
1684 #define WM5100_IN1L_VOL_MASK                    0x00FF  /* IN1L_VOL - [7:0] */
1685 #define WM5100_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [7:0] */
1686 #define WM5100_IN1L_VOL_WIDTH                        8  /* IN1L_VOL - [7:0] */
1689  * R801 (0x321) - ADC Digital Volume 1R
1694 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1698 #define WM5100_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
1699 #define WM5100_IN1R_VOL_MASK                    0x00FF  /* IN1R_VOL - [7:0] */
1700 #define WM5100_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [7:0] */
1701 #define WM5100_IN1R_VOL_WIDTH                        8  /* IN1R_VOL - [7:0] */
1704  * R802 (0x322) - ADC Digital Volume 2L
1709 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1713 #define WM5100_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
1714 #define WM5100_IN2L_VOL_MASK                    0x00FF  /* IN2L_VOL - [7:0] */
1715 #define WM5100_IN2L_VOL_SHIFT                        0  /* IN2L_VOL - [7:0] */
1716 #define WM5100_IN2L_VOL_WIDTH                        8  /* IN2L_VOL - [7:0] */
1719  * R803 (0x323) - ADC Digital Volume 2R
1724 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1728 #define WM5100_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
1729 #define WM5100_IN2R_VOL_MASK                    0x00FF  /* IN2R_VOL - [7:0] */
1730 #define WM5100_IN2R_VOL_SHIFT                        0  /* IN2R_VOL - [7:0] */
1731 #define WM5100_IN2R_VOL_WIDTH                        8  /* IN2R_VOL - [7:0] */
1734  * R804 (0x324) - ADC Digital Volume 3L
1739 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1743 #define WM5100_IN3L_MUTE_WIDTH                       1  /* IN3L_MUTE */
1744 #define WM5100_IN3L_VOL_MASK                    0x00FF  /* IN3L_VOL - [7:0] */
1745 #define WM5100_IN3L_VOL_SHIFT                        0  /* IN3L_VOL - [7:0] */
1746 #define WM5100_IN3L_VOL_WIDTH                        8  /* IN3L_VOL - [7:0] */
1749  * R805 (0x325) - ADC Digital Volume 3R
1754 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1758 #define WM5100_IN3R_MUTE_WIDTH                       1  /* IN3R_MUTE */
1759 #define WM5100_IN3R_VOL_MASK                    0x00FF  /* IN3R_VOL - [7:0] */
1760 #define WM5100_IN3R_VOL_SHIFT                        0  /* IN3R_VOL - [7:0] */
1761 #define WM5100_IN3R_VOL_WIDTH                        8  /* IN3R_VOL - [7:0] */
1764  * R806 (0x326) - ADC Digital Volume 4L
1769 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1773 #define WM5100_IN4L_MUTE_WIDTH                       1  /* IN4L_MUTE */
1774 #define WM5100_IN4L_VOL_MASK                    0x00FF  /* IN4L_VOL - [7:0] */
1775 #define WM5100_IN4L_VOL_SHIFT                        0  /* IN4L_VOL - [7:0] */
1776 #define WM5100_IN4L_VOL_WIDTH                        8  /* IN4L_VOL - [7:0] */
1779  * R807 (0x327) - ADC Digital Volume 4R
1784 #define WM5100_IN_VU_WIDTH                           1  /* IN_VU */
1788 #define WM5100_IN4R_MUTE_WIDTH                       1  /* IN4R_MUTE */
1789 #define WM5100_IN4R_VOL_MASK                    0x00FF  /* IN4R_VOL - [7:0] */
1790 #define WM5100_IN4R_VOL_SHIFT                        0  /* IN4R_VOL - [7:0] */
1791 #define WM5100_IN4R_VOL_WIDTH                        8  /* IN4R_VOL - [7:0] */
1794  * R1025 (0x401) - Output Enables 2
1799 #define WM5100_OUT6L_ENA_WIDTH                       1  /* OUT6L_ENA */
1803 #define WM5100_OUT6R_ENA_WIDTH                       1  /* OUT6R_ENA */
1807 #define WM5100_OUT5L_ENA_WIDTH                       1  /* OUT5L_ENA */
1811 #define WM5100_OUT5R_ENA_WIDTH                       1  /* OUT5R_ENA */
1815 #define WM5100_OUT4L_ENA_WIDTH                       1  /* OUT4L_ENA */
1819 #define WM5100_OUT4R_ENA_WIDTH                       1  /* OUT4R_ENA */
1822  * R1026 (0x402) - Output Status 1
1827 #define WM5100_OUT3L_ENA_STS_WIDTH                   1  /* OUT3L_ENA_STS */
1831 #define WM5100_OUT3R_ENA_STS_WIDTH                   1  /* OUT3R_ENA_STS */
1835 #define WM5100_OUT2L_ENA_STS_WIDTH                   1  /* OUT2L_ENA_STS */
1839 #define WM5100_OUT2R_ENA_STS_WIDTH                   1  /* OUT2R_ENA_STS */
1842 #define WM5100_OUT1L_ENA_STS_SHIFT                   1  /* OUT1L_ENA_STS */
1843 #define WM5100_OUT1L_ENA_STS_WIDTH                   1  /* OUT1L_ENA_STS */
1847 #define WM5100_OUT1R_ENA_STS_WIDTH                   1  /* OUT1R_ENA_STS */
1850  * R1027 (0x403) - Output Status 2
1855 #define WM5100_OUT6L_ENA_STS_WIDTH                   1  /* OUT6L_ENA_STS */
1859 #define WM5100_OUT6R_ENA_STS_WIDTH                   1  /* OUT6R_ENA_STS */
1863 #define WM5100_OUT5L_ENA_STS_WIDTH                   1  /* OUT5L_ENA_STS */
1867 #define WM5100_OUT5R_ENA_STS_WIDTH                   1  /* OUT5R_ENA_STS */
1871 #define WM5100_OUT4L_ENA_STS_WIDTH                   1  /* OUT4L_ENA_STS */
1875 #define WM5100_OUT4R_ENA_STS_WIDTH                   1  /* OUT4R_ENA_STS */
1878  * R1032 (0x408) - Channel Enables 1
1883 #define WM5100_HP3L_ENA_WIDTH                        1  /* HP3L_ENA */
1887 #define WM5100_HP3R_ENA_WIDTH                        1  /* HP3R_ENA */
1891 #define WM5100_HP2L_ENA_WIDTH                        1  /* HP2L_ENA */
1895 #define WM5100_HP2R_ENA_WIDTH                        1  /* HP2R_ENA */
1898 #define WM5100_HP1L_ENA_SHIFT                        1  /* HP1L_ENA */
1899 #define WM5100_HP1L_ENA_WIDTH                        1  /* HP1L_ENA */
1903 #define WM5100_HP1R_ENA_WIDTH                        1  /* HP1R_ENA */
1906  * R1040 (0x410) - Out Volume 1L
1908 #define WM5100_OUT_RATE_MASK                    0xC000  /* OUT_RATE - [15:14] */
1909 #define WM5100_OUT_RATE_SHIFT                       14  /* OUT_RATE - [15:14] */
1910 #define WM5100_OUT_RATE_WIDTH                        2  /* OUT_RATE - [15:14] */
1914 #define WM5100_OUT1_OSR_WIDTH                        1  /* OUT1_OSR */
1918 #define WM5100_OUT1_MONO_WIDTH                       1  /* OUT1_MONO */
1922 #define WM5100_OUT1L_ANC_SRC_WIDTH                   1  /* OUT1L_ANC_SRC */
1923 #define WM5100_OUT1L_PGA_VOL_MASK               0x00FE  /* OUT1L_PGA_VOL - [7:1] */
1924 #define WM5100_OUT1L_PGA_VOL_SHIFT                   1  /* OUT1L_PGA_VOL - [7:1] */
1925 #define WM5100_OUT1L_PGA_VOL_WIDTH                   7  /* OUT1L_PGA_VOL - [7:1] */
1928  * R1041 (0x411) - Out Volume 1R
1933 #define WM5100_OUT1R_ANC_SRC_WIDTH                   1  /* OUT1R_ANC_SRC */
1934 #define WM5100_OUT1R_PGA_VOL_MASK               0x00FE  /* OUT1R_PGA_VOL - [7:1] */
1935 #define WM5100_OUT1R_PGA_VOL_SHIFT                   1  /* OUT1R_PGA_VOL - [7:1] */
1936 #define WM5100_OUT1R_PGA_VOL_WIDTH                   7  /* OUT1R_PGA_VOL - [7:1] */
1939  * R1042 (0x412) - DAC Volume Limit 1L
1941 #define WM5100_OUT1L_VOL_LIM_MASK               0x00FF  /* OUT1L_VOL_LIM - [7:0] */
1942 #define WM5100_OUT1L_VOL_LIM_SHIFT                   0  /* OUT1L_VOL_LIM - [7:0] */
1943 #define WM5100_OUT1L_VOL_LIM_WIDTH                   8  /* OUT1L_VOL_LIM - [7:0] */
1946  * R1043 (0x413) - DAC Volume Limit 1R
1948 #define WM5100_OUT1R_VOL_LIM_MASK               0x00FF  /* OUT1R_VOL_LIM - [7:0] */
1949 #define WM5100_OUT1R_VOL_LIM_SHIFT                   0  /* OUT1R_VOL_LIM - [7:0] */
1950 #define WM5100_OUT1R_VOL_LIM_WIDTH                   8  /* OUT1R_VOL_LIM - [7:0] */
1953  * R1044 (0x414) - Out Volume 2L
1958 #define WM5100_OUT2_OSR_WIDTH                        1  /* OUT2_OSR */
1962 #define WM5100_OUT2_MONO_WIDTH                       1  /* OUT2_MONO */
1966 #define WM5100_OUT2L_ANC_SRC_WIDTH                   1  /* OUT2L_ANC_SRC */
1967 #define WM5100_OUT2L_PGA_VOL_MASK               0x00FE  /* OUT2L_PGA_VOL - [7:1] */
1968 #define WM5100_OUT2L_PGA_VOL_SHIFT                   1  /* OUT2L_PGA_VOL - [7:1] */
1969 #define WM5100_OUT2L_PGA_VOL_WIDTH                   7  /* OUT2L_PGA_VOL - [7:1] */
1972  * R1045 (0x415) - Out Volume 2R
1977 #define WM5100_OUT2R_ANC_SRC_WIDTH                   1  /* OUT2R_ANC_SRC */
1978 #define WM5100_OUT2R_PGA_VOL_MASK               0x00FE  /* OUT2R_PGA_VOL - [7:1] */
1979 #define WM5100_OUT2R_PGA_VOL_SHIFT                   1  /* OUT2R_PGA_VOL - [7:1] */
1980 #define WM5100_OUT2R_PGA_VOL_WIDTH                   7  /* OUT2R_PGA_VOL - [7:1] */
1983  * R1046 (0x416) - DAC Volume Limit 2L
1985 #define WM5100_OUT2L_VOL_LIM_MASK               0x00FF  /* OUT2L_VOL_LIM - [7:0] */
1986 #define WM5100_OUT2L_VOL_LIM_SHIFT                   0  /* OUT2L_VOL_LIM - [7:0] */
1987 #define WM5100_OUT2L_VOL_LIM_WIDTH                   8  /* OUT2L_VOL_LIM - [7:0] */
1990  * R1047 (0x417) - DAC Volume Limit 2R
1992 #define WM5100_OUT2R_VOL_LIM_MASK               0x00FF  /* OUT2R_VOL_LIM - [7:0] */
1993 #define WM5100_OUT2R_VOL_LIM_SHIFT                   0  /* OUT2R_VOL_LIM - [7:0] */
1994 #define WM5100_OUT2R_VOL_LIM_WIDTH                   8  /* OUT2R_VOL_LIM - [7:0] */
1997  * R1048 (0x418) - Out Volume 3L
2002 #define WM5100_OUT3_OSR_WIDTH                        1  /* OUT3_OSR */
2006 #define WM5100_OUT3_MONO_WIDTH                       1  /* OUT3_MONO */
2010 #define WM5100_OUT3L_ANC_SRC_WIDTH                   1  /* OUT3L_ANC_SRC */
2011 #define WM5100_OUT3L_PGA_VOL_MASK               0x00FE  /* OUT3L_PGA_VOL - [7:1] */
2012 #define WM5100_OUT3L_PGA_VOL_SHIFT                   1  /* OUT3L_PGA_VOL - [7:1] */
2013 #define WM5100_OUT3L_PGA_VOL_WIDTH                   7  /* OUT3L_PGA_VOL - [7:1] */
2016  * R1049 (0x419) - Out Volume 3R
2021 #define WM5100_OUT3R_ANC_SRC_WIDTH                   1  /* OUT3R_ANC_SRC */
2022 #define WM5100_OUT3R_PGA_VOL_MASK               0x00FE  /* OUT3R_PGA_VOL - [7:1] */
2023 #define WM5100_OUT3R_PGA_VOL_SHIFT                   1  /* OUT3R_PGA_VOL - [7:1] */
2024 #define WM5100_OUT3R_PGA_VOL_WIDTH                   7  /* OUT3R_PGA_VOL - [7:1] */
2027  * R1050 (0x41A) - DAC Volume Limit 3L
2029 #define WM5100_OUT3L_VOL_LIM_MASK               0x00FF  /* OUT3L_VOL_LIM - [7:0] */
2030 #define WM5100_OUT3L_VOL_LIM_SHIFT                   0  /* OUT3L_VOL_LIM - [7:0] */
2031 #define WM5100_OUT3L_VOL_LIM_WIDTH                   8  /* OUT3L_VOL_LIM - [7:0] */
2034  * R1051 (0x41B) - DAC Volume Limit 3R
2036 #define WM5100_OUT3R_VOL_LIM_MASK               0x00FF  /* OUT3R_VOL_LIM - [7:0] */
2037 #define WM5100_OUT3R_VOL_LIM_SHIFT                   0  /* OUT3R_VOL_LIM - [7:0] */
2038 #define WM5100_OUT3R_VOL_LIM_WIDTH                   8  /* OUT3R_VOL_LIM - [7:0] */
2041  * R1052 (0x41C) - Out Volume 4L
2046 #define WM5100_OUT4_OSR_WIDTH                        1  /* OUT4_OSR */
2050 #define WM5100_OUT4L_ANC_SRC_WIDTH                   1  /* OUT4L_ANC_SRC */
2051 #define WM5100_OUT4L_VOL_LIM_MASK               0x00FF  /* OUT4L_VOL_LIM - [7:0] */
2052 #define WM5100_OUT4L_VOL_LIM_SHIFT                   0  /* OUT4L_VOL_LIM - [7:0] */
2053 #define WM5100_OUT4L_VOL_LIM_WIDTH                   8  /* OUT4L_VOL_LIM - [7:0] */
2056  * R1053 (0x41D) - Out Volume 4R
2061 #define WM5100_OUT4R_ANC_SRC_WIDTH                   1  /* OUT4R_ANC_SRC */
2062 #define WM5100_OUT4R_VOL_LIM_MASK               0x00FF  /* OUT4R_VOL_LIM - [7:0] */
2063 #define WM5100_OUT4R_VOL_LIM_SHIFT                   0  /* OUT4R_VOL_LIM - [7:0] */
2064 #define WM5100_OUT4R_VOL_LIM_WIDTH                   8  /* OUT4R_VOL_LIM - [7:0] */
2067  * R1054 (0x41E) - DAC Volume Limit 5L
2072 #define WM5100_OUT5_OSR_WIDTH                        1  /* OUT5_OSR */
2076 #define WM5100_OUT5L_ANC_SRC_WIDTH                   1  /* OUT5L_ANC_SRC */
2077 #define WM5100_OUT5L_VOL_LIM_MASK               0x00FF  /* OUT5L_VOL_LIM - [7:0] */
2078 #define WM5100_OUT5L_VOL_LIM_SHIFT                   0  /* OUT5L_VOL_LIM - [7:0] */
2079 #define WM5100_OUT5L_VOL_LIM_WIDTH                   8  /* OUT5L_VOL_LIM - [7:0] */
2082  * R1055 (0x41F) - DAC Volume Limit 5R
2087 #define WM5100_OUT5R_ANC_SRC_WIDTH                   1  /* OUT5R_ANC_SRC */
2088 #define WM5100_OUT5R_VOL_LIM_MASK               0x00FF  /* OUT5R_VOL_LIM - [7:0] */
2089 #define WM5100_OUT5R_VOL_LIM_SHIFT                   0  /* OUT5R_VOL_LIM - [7:0] */
2090 #define WM5100_OUT5R_VOL_LIM_WIDTH                   8  /* OUT5R_VOL_LIM - [7:0] */
2093  * R1056 (0x420) - DAC Volume Limit 6L
2098 #define WM5100_OUT6_OSR_WIDTH                        1  /* OUT6_OSR */
2102 #define WM5100_OUT6L_ANC_SRC_WIDTH                   1  /* OUT6L_ANC_SRC */
2103 #define WM5100_OUT6L_VOL_LIM_MASK               0x00FF  /* OUT6L_VOL_LIM - [7:0] */
2104 #define WM5100_OUT6L_VOL_LIM_SHIFT                   0  /* OUT6L_VOL_LIM - [7:0] */
2105 #define WM5100_OUT6L_VOL_LIM_WIDTH                   8  /* OUT6L_VOL_LIM - [7:0] */
2108  * R1057 (0x421) - DAC Volume Limit 6R
2113 #define WM5100_OUT6R_ANC_SRC_WIDTH                   1  /* OUT6R_ANC_SRC */
2114 #define WM5100_OUT6R_VOL_LIM_MASK               0x00FF  /* OUT6R_VOL_LIM - [7:0] */
2115 #define WM5100_OUT6R_VOL_LIM_SHIFT                   0  /* OUT6R_VOL_LIM - [7:0] */
2116 #define WM5100_OUT6R_VOL_LIM_WIDTH                   8  /* OUT6R_VOL_LIM - [7:0] */
2119  * R1088 (0x440) - DAC AEC Control 1
2121 #define WM5100_AEC_LOOPBACK_SRC_MASK            0x003C  /* AEC_LOOPBACK_SRC - [5:2] */
2122 #define WM5100_AEC_LOOPBACK_SRC_SHIFT                2  /* AEC_LOOPBACK_SRC - [5:2] */
2123 #define WM5100_AEC_LOOPBACK_SRC_WIDTH                4  /* AEC_LOOPBACK_SRC - [5:2] */
2126 #define WM5100_AEC_ENA_STS_SHIFT                     1  /* AEC_ENA_STS */
2127 #define WM5100_AEC_ENA_STS_WIDTH                     1  /* AEC_ENA_STS */
2131 #define WM5100_AEC_LOOPBACK_ENA_WIDTH                1  /* AEC_LOOPBACK_ENA */
2134  * R1089 (0x441) - Output Volume Ramp
2136 #define WM5100_OUT_VD_RAMP_MASK                 0x0070  /* OUT_VD_RAMP - [6:4] */
2137 #define WM5100_OUT_VD_RAMP_SHIFT                     4  /* OUT_VD_RAMP - [6:4] */
2138 #define WM5100_OUT_VD_RAMP_WIDTH                     3  /* OUT_VD_RAMP - [6:4] */
2139 #define WM5100_OUT_VI_RAMP_MASK                 0x0007  /* OUT_VI_RAMP - [2:0] */
2140 #define WM5100_OUT_VI_RAMP_SHIFT                     0  /* OUT_VI_RAMP - [2:0] */
2141 #define WM5100_OUT_VI_RAMP_WIDTH                     3  /* OUT_VI_RAMP - [2:0] */
2144  * R1152 (0x480) - DAC Digital Volume 1L
2149 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2153 #define WM5100_OUT1L_MUTE_WIDTH                      1  /* OUT1L_MUTE */
2154 #define WM5100_OUT1L_VOL_MASK                   0x00FF  /* OUT1L_VOL - [7:0] */
2155 #define WM5100_OUT1L_VOL_SHIFT                       0  /* OUT1L_VOL - [7:0] */
2156 #define WM5100_OUT1L_VOL_WIDTH                       8  /* OUT1L_VOL - [7:0] */
2159  * R1153 (0x481) - DAC Digital Volume 1R
2164 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2168 #define WM5100_OUT1R_MUTE_WIDTH                      1  /* OUT1R_MUTE */
2169 #define WM5100_OUT1R_VOL_MASK                   0x00FF  /* OUT1R_VOL - [7:0] */
2170 #define WM5100_OUT1R_VOL_SHIFT                       0  /* OUT1R_VOL - [7:0] */
2171 #define WM5100_OUT1R_VOL_WIDTH                       8  /* OUT1R_VOL - [7:0] */
2174  * R1154 (0x482) - DAC Digital Volume 2L
2179 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2183 #define WM5100_OUT2L_MUTE_WIDTH                      1  /* OUT2L_MUTE */
2184 #define WM5100_OUT2L_VOL_MASK                   0x00FF  /* OUT2L_VOL - [7:0] */
2185 #define WM5100_OUT2L_VOL_SHIFT                       0  /* OUT2L_VOL - [7:0] */
2186 #define WM5100_OUT2L_VOL_WIDTH                       8  /* OUT2L_VOL - [7:0] */
2189  * R1155 (0x483) - DAC Digital Volume 2R
2194 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2198 #define WM5100_OUT2R_MUTE_WIDTH                      1  /* OUT2R_MUTE */
2199 #define WM5100_OUT2R_VOL_MASK                   0x00FF  /* OUT2R_VOL - [7:0] */
2200 #define WM5100_OUT2R_VOL_SHIFT                       0  /* OUT2R_VOL - [7:0] */
2201 #define WM5100_OUT2R_VOL_WIDTH                       8  /* OUT2R_VOL - [7:0] */
2204  * R1156 (0x484) - DAC Digital Volume 3L
2209 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2213 #define WM5100_OUT3L_MUTE_WIDTH                      1  /* OUT3L_MUTE */
2214 #define WM5100_OUT3L_VOL_MASK                   0x00FF  /* OUT3L_VOL - [7:0] */
2215 #define WM5100_OUT3L_VOL_SHIFT                       0  /* OUT3L_VOL - [7:0] */
2216 #define WM5100_OUT3L_VOL_WIDTH                       8  /* OUT3L_VOL - [7:0] */
2219  * R1157 (0x485) - DAC Digital Volume 3R
2224 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2228 #define WM5100_OUT3R_MUTE_WIDTH                      1  /* OUT3R_MUTE */
2229 #define WM5100_OUT3R_VOL_MASK                   0x00FF  /* OUT3R_VOL - [7:0] */
2230 #define WM5100_OUT3R_VOL_SHIFT                       0  /* OUT3R_VOL - [7:0] */
2231 #define WM5100_OUT3R_VOL_WIDTH                       8  /* OUT3R_VOL - [7:0] */
2234  * R1158 (0x486) - DAC Digital Volume 4L
2239 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2243 #define WM5100_OUT4L_MUTE_WIDTH                      1  /* OUT4L_MUTE */
2244 #define WM5100_OUT4L_VOL_MASK                   0x00FF  /* OUT4L_VOL - [7:0] */
2245 #define WM5100_OUT4L_VOL_SHIFT                       0  /* OUT4L_VOL - [7:0] */
2246 #define WM5100_OUT4L_VOL_WIDTH                       8  /* OUT4L_VOL - [7:0] */
2249  * R1159 (0x487) - DAC Digital Volume 4R
2254 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2258 #define WM5100_OUT4R_MUTE_WIDTH                      1  /* OUT4R_MUTE */
2259 #define WM5100_OUT4R_VOL_MASK                   0x00FF  /* OUT4R_VOL - [7:0] */
2260 #define WM5100_OUT4R_VOL_SHIFT                       0  /* OUT4R_VOL - [7:0] */
2261 #define WM5100_OUT4R_VOL_WIDTH                       8  /* OUT4R_VOL - [7:0] */
2264  * R1160 (0x488) - DAC Digital Volume 5L
2269 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2273 #define WM5100_OUT5L_MUTE_WIDTH                      1  /* OUT5L_MUTE */
2274 #define WM5100_OUT5L_VOL_MASK                   0x00FF  /* OUT5L_VOL - [7:0] */
2275 #define WM5100_OUT5L_VOL_SHIFT                       0  /* OUT5L_VOL - [7:0] */
2276 #define WM5100_OUT5L_VOL_WIDTH                       8  /* OUT5L_VOL - [7:0] */
2279  * R1161 (0x489) - DAC Digital Volume 5R
2284 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2288 #define WM5100_OUT5R_MUTE_WIDTH                      1  /* OUT5R_MUTE */
2289 #define WM5100_OUT5R_VOL_MASK                   0x00FF  /* OUT5R_VOL - [7:0] */
2290 #define WM5100_OUT5R_VOL_SHIFT                       0  /* OUT5R_VOL - [7:0] */
2291 #define WM5100_OUT5R_VOL_WIDTH                       8  /* OUT5R_VOL - [7:0] */
2294  * R1162 (0x48A) - DAC Digital Volume 6L
2299 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2303 #define WM5100_OUT6L_MUTE_WIDTH                      1  /* OUT6L_MUTE */
2304 #define WM5100_OUT6L_VOL_MASK                   0x00FF  /* OUT6L_VOL - [7:0] */
2305 #define WM5100_OUT6L_VOL_SHIFT                       0  /* OUT6L_VOL - [7:0] */
2306 #define WM5100_OUT6L_VOL_WIDTH                       8  /* OUT6L_VOL - [7:0] */
2309  * R1163 (0x48B) - DAC Digital Volume 6R
2314 #define WM5100_OUT_VU_WIDTH                          1  /* OUT_VU */
2318 #define WM5100_OUT6R_MUTE_WIDTH                      1  /* OUT6R_MUTE */
2319 #define WM5100_OUT6R_VOL_MASK                   0x00FF  /* OUT6R_VOL - [7:0] */
2320 #define WM5100_OUT6R_VOL_SHIFT                       0  /* OUT6R_VOL - [7:0] */
2321 #define WM5100_OUT6R_VOL_WIDTH                       8  /* OUT6R_VOL - [7:0] */
2324  * R1216 (0x4C0) - PDM SPK1 CTRL 1
2329 #define WM5100_SPK1R_MUTE_WIDTH                      1  /* SPK1R_MUTE */
2333 #define WM5100_SPK1L_MUTE_WIDTH                      1  /* SPK1L_MUTE */
2337 #define WM5100_SPK1_MUTE_ENDIAN_WIDTH                1  /* SPK1_MUTE_ENDIAN */
2338 #define WM5100_SPK1_MUTE_SEQ1_MASK              0x00FF  /* SPK1_MUTE_SEQ1 - [7:0] */
2339 #define WM5100_SPK1_MUTE_SEQ1_SHIFT                  0  /* SPK1_MUTE_SEQ1 - [7:0] */
2340 #define WM5100_SPK1_MUTE_SEQ1_WIDTH                  8  /* SPK1_MUTE_SEQ1 - [7:0] */
2343  * R1217 (0x4C1) - PDM SPK1 CTRL 2
2348 #define WM5100_SPK1_FMT_WIDTH                        1  /* SPK1_FMT */
2351  * R1218 (0x4C2) - PDM SPK2 CTRL 1
2356 #define WM5100_SPK2R_MUTE_WIDTH                      1  /* SPK2R_MUTE */
2360 #define WM5100_SPK2L_MUTE_WIDTH                      1  /* SPK2L_MUTE */
2364 #define WM5100_SPK2_MUTE_ENDIAN_WIDTH                1  /* SPK2_MUTE_ENDIAN */
2365 #define WM5100_SPK2_MUTE_SEQ1_MASK              0x00FF  /* SPK2_MUTE_SEQ1 - [7:0] */
2366 #define WM5100_SPK2_MUTE_SEQ1_SHIFT                  0  /* SPK2_MUTE_SEQ1 - [7:0] */
2367 #define WM5100_SPK2_MUTE_SEQ1_WIDTH                  8  /* SPK2_MUTE_SEQ1 - [7:0] */
2370  * R1219 (0x4C3) - PDM SPK2 CTRL 2
2375 #define WM5100_SPK2_FMT_WIDTH                        1  /* SPK2_FMT */
2378  * R1280 (0x500) - Audio IF 1_1
2383 #define WM5100_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
2387 #define WM5100_AIF1_BCLK_FRC_WIDTH                   1  /* AIF1_BCLK_FRC */
2391 #define WM5100_AIF1_BCLK_MSTR_WIDTH                  1  /* AIF1_BCLK_MSTR */
2392 #define WM5100_AIF1_BCLK_FREQ_MASK              0x001F  /* AIF1_BCLK_FREQ - [4:0] */
2393 #define WM5100_AIF1_BCLK_FREQ_SHIFT                  0  /* AIF1_BCLK_FREQ - [4:0] */
2394 #define WM5100_AIF1_BCLK_FREQ_WIDTH                  5  /* AIF1_BCLK_FREQ - [4:0] */
2397  * R1281 (0x501) - Audio IF 1_2
2402 #define WM5100_AIF1TX_DAT_TRI_WIDTH                  1  /* AIF1TX_DAT_TRI */
2406 #define WM5100_AIF1TX_LRCLK_SRC_WIDTH                1  /* AIF1TX_LRCLK_SRC */
2410 #define WM5100_AIF1TX_LRCLK_INV_WIDTH                1  /* AIF1TX_LRCLK_INV */
2413 #define WM5100_AIF1TX_LRCLK_FRC_SHIFT                1  /* AIF1TX_LRCLK_FRC */
2414 #define WM5100_AIF1TX_LRCLK_FRC_WIDTH                1  /* AIF1TX_LRCLK_FRC */
2418 #define WM5100_AIF1TX_LRCLK_MSTR_WIDTH               1  /* AIF1TX_LRCLK_MSTR */
2421  * R1282 (0x502) - Audio IF 1_3
2426 #define WM5100_AIF1RX_LRCLK_INV_WIDTH                1  /* AIF1RX_LRCLK_INV */
2429 #define WM5100_AIF1RX_LRCLK_FRC_SHIFT                1  /* AIF1RX_LRCLK_FRC */
2430 #define WM5100_AIF1RX_LRCLK_FRC_WIDTH                1  /* AIF1RX_LRCLK_FRC */
2434 #define WM5100_AIF1RX_LRCLK_MSTR_WIDTH               1  /* AIF1RX_LRCLK_MSTR */
2437  * R1283 (0x503) - Audio IF 1_4
2442 #define WM5100_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
2443 #define WM5100_AIF1_RATE_MASK                   0x0003  /* AIF1_RATE - [1:0] */
2444 #define WM5100_AIF1_RATE_SHIFT                       0  /* AIF1_RATE - [1:0] */
2445 #define WM5100_AIF1_RATE_WIDTH                       2  /* AIF1_RATE - [1:0] */
2448  * R1284 (0x504) - Audio IF 1_5
2450 #define WM5100_AIF1_FMT_MASK                    0x0007  /* AIF1_FMT - [2:0] */
2451 #define WM5100_AIF1_FMT_SHIFT                        0  /* AIF1_FMT - [2:0] */
2452 #define WM5100_AIF1_FMT_WIDTH                        3  /* AIF1_FMT - [2:0] */
2455  * R1285 (0x505) - Audio IF 1_6
2457 #define WM5100_AIF1TX_BCPF_MASK                 0x1FFF  /* AIF1TX_BCPF - [12:0] */
2458 #define WM5100_AIF1TX_BCPF_SHIFT                     0  /* AIF1TX_BCPF - [12:0] */
2459 #define WM5100_AIF1TX_BCPF_WIDTH                    13  /* AIF1TX_BCPF - [12:0] */
2462  * R1286 (0x506) - Audio IF 1_7
2464 #define WM5100_AIF1RX_BCPF_MASK                 0x1FFF  /* AIF1RX_BCPF - [12:0] */
2465 #define WM5100_AIF1RX_BCPF_SHIFT                     0  /* AIF1RX_BCPF - [12:0] */
2466 #define WM5100_AIF1RX_BCPF_WIDTH                    13  /* AIF1RX_BCPF - [12:0] */
2469  * R1287 (0x507) - Audio IF 1_8
2471 #define WM5100_AIF1TX_WL_MASK                   0x3F00  /* AIF1TX_WL - [13:8] */
2472 #define WM5100_AIF1TX_WL_SHIFT                       8  /* AIF1TX_WL - [13:8] */
2473 #define WM5100_AIF1TX_WL_WIDTH                       6  /* AIF1TX_WL - [13:8] */
2474 #define WM5100_AIF1TX_SLOT_LEN_MASK             0x00FF  /* AIF1TX_SLOT_LEN - [7:0] */
2475 #define WM5100_AIF1TX_SLOT_LEN_SHIFT                 0  /* AIF1TX_SLOT_LEN - [7:0] */
2476 #define WM5100_AIF1TX_SLOT_LEN_WIDTH                 8  /* AIF1TX_SLOT_LEN - [7:0] */
2479  * R1288 (0x508) - Audio IF 1_9
2481 #define WM5100_AIF1RX_WL_MASK                   0x3F00  /* AIF1RX_WL - [13:8] */
2482 #define WM5100_AIF1RX_WL_SHIFT                       8  /* AIF1RX_WL - [13:8] */
2483 #define WM5100_AIF1RX_WL_WIDTH                       6  /* AIF1RX_WL - [13:8] */
2484 #define WM5100_AIF1RX_SLOT_LEN_MASK             0x00FF  /* AIF1RX_SLOT_LEN - [7:0] */
2485 #define WM5100_AIF1RX_SLOT_LEN_SHIFT                 0  /* AIF1RX_SLOT_LEN - [7:0] */
2486 #define WM5100_AIF1RX_SLOT_LEN_WIDTH                 8  /* AIF1RX_SLOT_LEN - [7:0] */
2489  * R1289 (0x509) - Audio IF 1_10
2491 #define WM5100_AIF1TX1_SLOT_MASK                0x003F  /* AIF1TX1_SLOT - [5:0] */
2492 #define WM5100_AIF1TX1_SLOT_SHIFT                    0  /* AIF1TX1_SLOT - [5:0] */
2493 #define WM5100_AIF1TX1_SLOT_WIDTH                    6  /* AIF1TX1_SLOT - [5:0] */
2496  * R1290 (0x50A) - Audio IF 1_11
2498 #define WM5100_AIF1TX2_SLOT_MASK                0x003F  /* AIF1TX2_SLOT - [5:0] */
2499 #define WM5100_AIF1TX2_SLOT_SHIFT                    0  /* AIF1TX2_SLOT - [5:0] */
2500 #define WM5100_AIF1TX2_SLOT_WIDTH                    6  /* AIF1TX2_SLOT - [5:0] */
2503  * R1291 (0x50B) - Audio IF 1_12
2505 #define WM5100_AIF1TX3_SLOT_MASK                0x003F  /* AIF1TX3_SLOT - [5:0] */
2506 #define WM5100_AIF1TX3_SLOT_SHIFT                    0  /* AIF1TX3_SLOT - [5:0] */
2507 #define WM5100_AIF1TX3_SLOT_WIDTH                    6  /* AIF1TX3_SLOT - [5:0] */
2510  * R1292 (0x50C) - Audio IF 1_13
2512 #define WM5100_AIF1TX4_SLOT_MASK                0x003F  /* AIF1TX4_SLOT - [5:0] */
2513 #define WM5100_AIF1TX4_SLOT_SHIFT                    0  /* AIF1TX4_SLOT - [5:0] */
2514 #define WM5100_AIF1TX4_SLOT_WIDTH                    6  /* AIF1TX4_SLOT - [5:0] */
2517  * R1293 (0x50D) - Audio IF 1_14
2519 #define WM5100_AIF1TX5_SLOT_MASK                0x003F  /* AIF1TX5_SLOT - [5:0] */
2520 #define WM5100_AIF1TX5_SLOT_SHIFT                    0  /* AIF1TX5_SLOT - [5:0] */
2521 #define WM5100_AIF1TX5_SLOT_WIDTH                    6  /* AIF1TX5_SLOT - [5:0] */
2524  * R1294 (0x50E) - Audio IF 1_15
2526 #define WM5100_AIF1TX6_SLOT_MASK                0x003F  /* AIF1TX6_SLOT - [5:0] */
2527 #define WM5100_AIF1TX6_SLOT_SHIFT                    0  /* AIF1TX6_SLOT - [5:0] */
2528 #define WM5100_AIF1TX6_SLOT_WIDTH                    6  /* AIF1TX6_SLOT - [5:0] */
2531  * R1295 (0x50F) - Audio IF 1_16
2533 #define WM5100_AIF1TX7_SLOT_MASK                0x003F  /* AIF1TX7_SLOT - [5:0] */
2534 #define WM5100_AIF1TX7_SLOT_SHIFT                    0  /* AIF1TX7_SLOT - [5:0] */
2535 #define WM5100_AIF1TX7_SLOT_WIDTH                    6  /* AIF1TX7_SLOT - [5:0] */
2538  * R1296 (0x510) - Audio IF 1_17
2540 #define WM5100_AIF1TX8_SLOT_MASK                0x003F  /* AIF1TX8_SLOT - [5:0] */
2541 #define WM5100_AIF1TX8_SLOT_SHIFT                    0  /* AIF1TX8_SLOT - [5:0] */
2542 #define WM5100_AIF1TX8_SLOT_WIDTH                    6  /* AIF1TX8_SLOT - [5:0] */
2545  * R1297 (0x511) - Audio IF 1_18
2547 #define WM5100_AIF1RX1_SLOT_MASK                0x003F  /* AIF1RX1_SLOT - [5:0] */
2548 #define WM5100_AIF1RX1_SLOT_SHIFT                    0  /* AIF1RX1_SLOT - [5:0] */
2549 #define WM5100_AIF1RX1_SLOT_WIDTH                    6  /* AIF1RX1_SLOT - [5:0] */
2552  * R1298 (0x512) - Audio IF 1_19
2554 #define WM5100_AIF1RX2_SLOT_MASK                0x003F  /* AIF1RX2_SLOT - [5:0] */
2555 #define WM5100_AIF1RX2_SLOT_SHIFT                    0  /* AIF1RX2_SLOT - [5:0] */
2556 #define WM5100_AIF1RX2_SLOT_WIDTH                    6  /* AIF1RX2_SLOT - [5:0] */
2559  * R1299 (0x513) - Audio IF 1_20
2561 #define WM5100_AIF1RX3_SLOT_MASK                0x003F  /* AIF1RX3_SLOT - [5:0] */
2562 #define WM5100_AIF1RX3_SLOT_SHIFT                    0  /* AIF1RX3_SLOT - [5:0] */
2563 #define WM5100_AIF1RX3_SLOT_WIDTH                    6  /* AIF1RX3_SLOT - [5:0] */
2566  * R1300 (0x514) - Audio IF 1_21
2568 #define WM5100_AIF1RX4_SLOT_MASK                0x003F  /* AIF1RX4_SLOT - [5:0] */
2569 #define WM5100_AIF1RX4_SLOT_SHIFT                    0  /* AIF1RX4_SLOT - [5:0] */
2570 #define WM5100_AIF1RX4_SLOT_WIDTH                    6  /* AIF1RX4_SLOT - [5:0] */
2573  * R1301 (0x515) - Audio IF 1_22
2575 #define WM5100_AIF1RX5_SLOT_MASK                0x003F  /* AIF1RX5_SLOT - [5:0] */
2576 #define WM5100_AIF1RX5_SLOT_SHIFT                    0  /* AIF1RX5_SLOT - [5:0] */
2577 #define WM5100_AIF1RX5_SLOT_WIDTH                    6  /* AIF1RX5_SLOT - [5:0] */
2580  * R1302 (0x516) - Audio IF 1_23
2582 #define WM5100_AIF1RX6_SLOT_MASK                0x003F  /* AIF1RX6_SLOT - [5:0] */
2583 #define WM5100_AIF1RX6_SLOT_SHIFT                    0  /* AIF1RX6_SLOT - [5:0] */
2584 #define WM5100_AIF1RX6_SLOT_WIDTH                    6  /* AIF1RX6_SLOT - [5:0] */
2587  * R1303 (0x517) - Audio IF 1_24
2589 #define WM5100_AIF1RX7_SLOT_MASK                0x003F  /* AIF1RX7_SLOT - [5:0] */
2590 #define WM5100_AIF1RX7_SLOT_SHIFT                    0  /* AIF1RX7_SLOT - [5:0] */
2591 #define WM5100_AIF1RX7_SLOT_WIDTH                    6  /* AIF1RX7_SLOT - [5:0] */
2594  * R1304 (0x518) - Audio IF 1_25
2596 #define WM5100_AIF1RX8_SLOT_MASK                0x003F  /* AIF1RX8_SLOT - [5:0] */
2597 #define WM5100_AIF1RX8_SLOT_SHIFT                    0  /* AIF1RX8_SLOT - [5:0] */
2598 #define WM5100_AIF1RX8_SLOT_WIDTH                    6  /* AIF1RX8_SLOT - [5:0] */
2601  * R1305 (0x519) - Audio IF 1_26
2606 #define WM5100_AIF1TX8_ENA_WIDTH                     1  /* AIF1TX8_ENA */
2610 #define WM5100_AIF1TX7_ENA_WIDTH                     1  /* AIF1TX7_ENA */
2614 #define WM5100_AIF1TX6_ENA_WIDTH                     1  /* AIF1TX6_ENA */
2618 #define WM5100_AIF1TX5_ENA_WIDTH                     1  /* AIF1TX5_ENA */
2622 #define WM5100_AIF1TX4_ENA_WIDTH                     1  /* AIF1TX4_ENA */
2626 #define WM5100_AIF1TX3_ENA_WIDTH                     1  /* AIF1TX3_ENA */
2629 #define WM5100_AIF1TX2_ENA_SHIFT                     1  /* AIF1TX2_ENA */
2630 #define WM5100_AIF1TX2_ENA_WIDTH                     1  /* AIF1TX2_ENA */
2634 #define WM5100_AIF1TX1_ENA_WIDTH                     1  /* AIF1TX1_ENA */
2637  * R1306 (0x51A) - Audio IF 1_27
2642 #define WM5100_AIF1RX8_ENA_WIDTH                     1  /* AIF1RX8_ENA */
2646 #define WM5100_AIF1RX7_ENA_WIDTH                     1  /* AIF1RX7_ENA */
2650 #define WM5100_AIF1RX6_ENA_WIDTH                     1  /* AIF1RX6_ENA */
2654 #define WM5100_AIF1RX5_ENA_WIDTH                     1  /* AIF1RX5_ENA */
2658 #define WM5100_AIF1RX4_ENA_WIDTH                     1  /* AIF1RX4_ENA */
2662 #define WM5100_AIF1RX3_ENA_WIDTH                     1  /* AIF1RX3_ENA */
2665 #define WM5100_AIF1RX2_ENA_SHIFT                     1  /* AIF1RX2_ENA */
2666 #define WM5100_AIF1RX2_ENA_WIDTH                     1  /* AIF1RX2_ENA */
2670 #define WM5100_AIF1RX1_ENA_WIDTH                     1  /* AIF1RX1_ENA */
2673  * R1344 (0x540) - Audio IF 2_1
2678 #define WM5100_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
2682 #define WM5100_AIF2_BCLK_FRC_WIDTH                   1  /* AIF2_BCLK_FRC */
2686 #define WM5100_AIF2_BCLK_MSTR_WIDTH                  1  /* AIF2_BCLK_MSTR */
2687 #define WM5100_AIF2_BCLK_FREQ_MASK              0x001F  /* AIF2_BCLK_FREQ - [4:0] */
2688 #define WM5100_AIF2_BCLK_FREQ_SHIFT                  0  /* AIF2_BCLK_FREQ - [4:0] */
2689 #define WM5100_AIF2_BCLK_FREQ_WIDTH                  5  /* AIF2_BCLK_FREQ - [4:0] */
2692  * R1345 (0x541) - Audio IF 2_2
2697 #define WM5100_AIF2TX_DAT_TRI_WIDTH                  1  /* AIF2TX_DAT_TRI */
2701 #define WM5100_AIF2TX_LRCLK_SRC_WIDTH                1  /* AIF2TX_LRCLK_SRC */
2705 #define WM5100_AIF2TX_LRCLK_INV_WIDTH                1  /* AIF2TX_LRCLK_INV */
2708 #define WM5100_AIF2TX_LRCLK_FRC_SHIFT                1  /* AIF2TX_LRCLK_FRC */
2709 #define WM5100_AIF2TX_LRCLK_FRC_WIDTH                1  /* AIF2TX_LRCLK_FRC */
2713 #define WM5100_AIF2TX_LRCLK_MSTR_WIDTH               1  /* AIF2TX_LRCLK_MSTR */
2716  * R1346 (0x542) - Audio IF 2_3
2721 #define WM5100_AIF2RX_LRCLK_INV_WIDTH                1  /* AIF2RX_LRCLK_INV */
2724 #define WM5100_AIF2RX_LRCLK_FRC_SHIFT                1  /* AIF2RX_LRCLK_FRC */
2725 #define WM5100_AIF2RX_LRCLK_FRC_WIDTH                1  /* AIF2RX_LRCLK_FRC */
2729 #define WM5100_AIF2RX_LRCLK_MSTR_WIDTH               1  /* AIF2RX_LRCLK_MSTR */
2732  * R1347 (0x543) - Audio IF 2_4
2737 #define WM5100_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
2738 #define WM5100_AIF2_RATE_MASK                   0x0003  /* AIF2_RATE - [1:0] */
2739 #define WM5100_AIF2_RATE_SHIFT                       0  /* AIF2_RATE - [1:0] */
2740 #define WM5100_AIF2_RATE_WIDTH                       2  /* AIF2_RATE - [1:0] */
2743  * R1348 (0x544) - Audio IF 2_5
2745 #define WM5100_AIF2_FMT_MASK                    0x0007  /* AIF2_FMT - [2:0] */
2746 #define WM5100_AIF2_FMT_SHIFT                        0  /* AIF2_FMT - [2:0] */
2747 #define WM5100_AIF2_FMT_WIDTH                        3  /* AIF2_FMT - [2:0] */
2750  * R1349 (0x545) - Audio IF 2_6
2752 #define WM5100_AIF2TX_BCPF_MASK                 0x1FFF  /* AIF2TX_BCPF - [12:0] */
2753 #define WM5100_AIF2TX_BCPF_SHIFT                     0  /* AIF2TX_BCPF - [12:0] */
2754 #define WM5100_AIF2TX_BCPF_WIDTH                    13  /* AIF2TX_BCPF - [12:0] */
2757  * R1350 (0x546) - Audio IF 2_7
2759 #define WM5100_AIF2RX_BCPF_MASK                 0x1FFF  /* AIF2RX_BCPF - [12:0] */
2760 #define WM5100_AIF2RX_BCPF_SHIFT                     0  /* AIF2RX_BCPF - [12:0] */
2761 #define WM5100_AIF2RX_BCPF_WIDTH                    13  /* AIF2RX_BCPF - [12:0] */
2764  * R1351 (0x547) - Audio IF 2_8
2766 #define WM5100_AIF2TX_WL_MASK                   0x3F00  /* AIF2TX_WL - [13:8] */
2767 #define WM5100_AIF2TX_WL_SHIFT                       8  /* AIF2TX_WL - [13:8] */
2768 #define WM5100_AIF2TX_WL_WIDTH                       6  /* AIF2TX_WL - [13:8] */
2769 #define WM5100_AIF2TX_SLOT_LEN_MASK             0x00FF  /* AIF2TX_SLOT_LEN - [7:0] */
2770 #define WM5100_AIF2TX_SLOT_LEN_SHIFT                 0  /* AIF2TX_SLOT_LEN - [7:0] */
2771 #define WM5100_AIF2TX_SLOT_LEN_WIDTH                 8  /* AIF2TX_SLOT_LEN - [7:0] */
2774  * R1352 (0x548) - Audio IF 2_9
2776 #define WM5100_AIF2RX_WL_MASK                   0x3F00  /* AIF2RX_WL - [13:8] */
2777 #define WM5100_AIF2RX_WL_SHIFT                       8  /* AIF2RX_WL - [13:8] */
2778 #define WM5100_AIF2RX_WL_WIDTH                       6  /* AIF2RX_WL - [13:8] */
2779 #define WM5100_AIF2RX_SLOT_LEN_MASK             0x00FF  /* AIF2RX_SLOT_LEN - [7:0] */
2780 #define WM5100_AIF2RX_SLOT_LEN_SHIFT                 0  /* AIF2RX_SLOT_LEN - [7:0] */
2781 #define WM5100_AIF2RX_SLOT_LEN_WIDTH                 8  /* AIF2RX_SLOT_LEN - [7:0] */
2784  * R1353 (0x549) - Audio IF 2_10
2786 #define WM5100_AIF2TX1_SLOT_MASK                0x003F  /* AIF2TX1_SLOT - [5:0] */
2787 #define WM5100_AIF2TX1_SLOT_SHIFT                    0  /* AIF2TX1_SLOT - [5:0] */
2788 #define WM5100_AIF2TX1_SLOT_WIDTH                    6  /* AIF2TX1_SLOT - [5:0] */
2791  * R1354 (0x54A) - Audio IF 2_11
2793 #define WM5100_AIF2TX2_SLOT_MASK                0x003F  /* AIF2TX2_SLOT - [5:0] */
2794 #define WM5100_AIF2TX2_SLOT_SHIFT                    0  /* AIF2TX2_SLOT - [5:0] */
2795 #define WM5100_AIF2TX2_SLOT_WIDTH                    6  /* AIF2TX2_SLOT - [5:0] */
2798  * R1361 (0x551) - Audio IF 2_18
2800 #define WM5100_AIF2RX1_SLOT_MASK                0x003F  /* AIF2RX1_SLOT - [5:0] */
2801 #define WM5100_AIF2RX1_SLOT_SHIFT                    0  /* AIF2RX1_SLOT - [5:0] */
2802 #define WM5100_AIF2RX1_SLOT_WIDTH                    6  /* AIF2RX1_SLOT - [5:0] */
2805  * R1362 (0x552) - Audio IF 2_19
2807 #define WM5100_AIF2RX2_SLOT_MASK                0x003F  /* AIF2RX2_SLOT - [5:0] */
2808 #define WM5100_AIF2RX2_SLOT_SHIFT                    0  /* AIF2RX2_SLOT - [5:0] */
2809 #define WM5100_AIF2RX2_SLOT_WIDTH                    6  /* AIF2RX2_SLOT - [5:0] */
2812  * R1369 (0x559) - Audio IF 2_26
2816 #define WM5100_AIF2TX2_ENA_SHIFT                     1  /* AIF2TX2_ENA */
2817 #define WM5100_AIF2TX2_ENA_WIDTH                     1  /* AIF2TX2_ENA */
2821 #define WM5100_AIF2TX1_ENA_WIDTH                     1  /* AIF2TX1_ENA */
2824  * R1370 (0x55A) - Audio IF 2_27
2828 #define WM5100_AIF2RX2_ENA_SHIFT                     1  /* AIF2RX2_ENA */
2829 #define WM5100_AIF2RX2_ENA_WIDTH                     1  /* AIF2RX2_ENA */
2833 #define WM5100_AIF2RX1_ENA_WIDTH                     1  /* AIF2RX1_ENA */
2836  * R1408 (0x580) - Audio IF 3_1
2841 #define WM5100_AIF3_BCLK_INV_WIDTH                   1  /* AIF3_BCLK_INV */
2845 #define WM5100_AIF3_BCLK_FRC_WIDTH                   1  /* AIF3_BCLK_FRC */
2849 #define WM5100_AIF3_BCLK_MSTR_WIDTH                  1  /* AIF3_BCLK_MSTR */
2850 #define WM5100_AIF3_BCLK_FREQ_MASK              0x001F  /* AIF3_BCLK_FREQ - [4:0] */
2851 #define WM5100_AIF3_BCLK_FREQ_SHIFT                  0  /* AIF3_BCLK_FREQ - [4:0] */
2852 #define WM5100_AIF3_BCLK_FREQ_WIDTH                  5  /* AIF3_BCLK_FREQ - [4:0] */
2855  * R1409 (0x581) - Audio IF 3_2
2860 #define WM5100_AIF3TX_DAT_TRI_WIDTH                  1  /* AIF3TX_DAT_TRI */
2864 #define WM5100_AIF3TX_LRCLK_SRC_WIDTH                1  /* AIF3TX_LRCLK_SRC */
2868 #define WM5100_AIF3TX_LRCLK_INV_WIDTH                1  /* AIF3TX_LRCLK_INV */
2871 #define WM5100_AIF3TX_LRCLK_FRC_SHIFT                1  /* AIF3TX_LRCLK_FRC */
2872 #define WM5100_AIF3TX_LRCLK_FRC_WIDTH                1  /* AIF3TX_LRCLK_FRC */
2876 #define WM5100_AIF3TX_LRCLK_MSTR_WIDTH               1  /* AIF3TX_LRCLK_MSTR */
2879  * R1410 (0x582) - Audio IF 3_3
2884 #define WM5100_AIF3RX_LRCLK_INV_WIDTH                1  /* AIF3RX_LRCLK_INV */
2887 #define WM5100_AIF3RX_LRCLK_FRC_SHIFT                1  /* AIF3RX_LRCLK_FRC */
2888 #define WM5100_AIF3RX_LRCLK_FRC_WIDTH                1  /* AIF3RX_LRCLK_FRC */
2892 #define WM5100_AIF3RX_LRCLK_MSTR_WIDTH               1  /* AIF3RX_LRCLK_MSTR */
2895  * R1411 (0x583) - Audio IF 3_4
2900 #define WM5100_AIF3_TRI_WIDTH                        1  /* AIF3_TRI */
2901 #define WM5100_AIF3_RATE_MASK                   0x0003  /* AIF3_RATE - [1:0] */
2902 #define WM5100_AIF3_RATE_SHIFT                       0  /* AIF3_RATE - [1:0] */
2903 #define WM5100_AIF3_RATE_WIDTH                       2  /* AIF3_RATE - [1:0] */
2906  * R1412 (0x584) - Audio IF 3_5
2908 #define WM5100_AIF3_FMT_MASK                    0x0007  /* AIF3_FMT - [2:0] */
2909 #define WM5100_AIF3_FMT_SHIFT                        0  /* AIF3_FMT - [2:0] */
2910 #define WM5100_AIF3_FMT_WIDTH                        3  /* AIF3_FMT - [2:0] */
2913  * R1413 (0x585) - Audio IF 3_6
2915 #define WM5100_AIF3TX_BCPF_MASK                 0x1FFF  /* AIF3TX_BCPF - [12:0] */
2916 #define WM5100_AIF3TX_BCPF_SHIFT                     0  /* AIF3TX_BCPF - [12:0] */
2917 #define WM5100_AIF3TX_BCPF_WIDTH                    13  /* AIF3TX_BCPF - [12:0] */
2920  * R1414 (0x586) - Audio IF 3_7
2922 #define WM5100_AIF3RX_BCPF_MASK                 0x1FFF  /* AIF3RX_BCPF - [12:0] */
2923 #define WM5100_AIF3RX_BCPF_SHIFT                     0  /* AIF3RX_BCPF - [12:0] */
2924 #define WM5100_AIF3RX_BCPF_WIDTH                    13  /* AIF3RX_BCPF - [12:0] */
2927  * R1415 (0x587) - Audio IF 3_8
2929 #define WM5100_AIF3TX_WL_MASK                   0x3F00  /* AIF3TX_WL - [13:8] */
2930 #define WM5100_AIF3TX_WL_SHIFT                       8  /* AIF3TX_WL - [13:8] */
2931 #define WM5100_AIF3TX_WL_WIDTH                       6  /* AIF3TX_WL - [13:8] */
2932 #define WM5100_AIF3TX_SLOT_LEN_MASK             0x00FF  /* AIF3TX_SLOT_LEN - [7:0] */
2933 #define WM5100_AIF3TX_SLOT_LEN_SHIFT                 0  /* AIF3TX_SLOT_LEN - [7:0] */
2934 #define WM5100_AIF3TX_SLOT_LEN_WIDTH                 8  /* AIF3TX_SLOT_LEN - [7:0] */
2937  * R1416 (0x588) - Audio IF 3_9
2939 #define WM5100_AIF3RX_WL_MASK                   0x3F00  /* AIF3RX_WL - [13:8] */
2940 #define WM5100_AIF3RX_WL_SHIFT                       8  /* AIF3RX_WL - [13:8] */
2941 #define WM5100_AIF3RX_WL_WIDTH                       6  /* AIF3RX_WL - [13:8] */
2942 #define WM5100_AIF3RX_SLOT_LEN_MASK             0x00FF  /* AIF3RX_SLOT_LEN - [7:0] */
2943 #define WM5100_AIF3RX_SLOT_LEN_SHIFT                 0  /* AIF3RX_SLOT_LEN - [7:0] */
2944 #define WM5100_AIF3RX_SLOT_LEN_WIDTH                 8  /* AIF3RX_SLOT_LEN - [7:0] */
2947  * R1417 (0x589) - Audio IF 3_10
2949 #define WM5100_AIF3TX1_SLOT_MASK                0x003F  /* AIF3TX1_SLOT - [5:0] */
2950 #define WM5100_AIF3TX1_SLOT_SHIFT                    0  /* AIF3TX1_SLOT - [5:0] */
2951 #define WM5100_AIF3TX1_SLOT_WIDTH                    6  /* AIF3TX1_SLOT - [5:0] */
2954  * R1418 (0x58A) - Audio IF 3_11
2956 #define WM5100_AIF3TX2_SLOT_MASK                0x003F  /* AIF3TX2_SLOT - [5:0] */
2957 #define WM5100_AIF3TX2_SLOT_SHIFT                    0  /* AIF3TX2_SLOT - [5:0] */
2958 #define WM5100_AIF3TX2_SLOT_WIDTH                    6  /* AIF3TX2_SLOT - [5:0] */
2961  * R1425 (0x591) - Audio IF 3_18
2963 #define WM5100_AIF3RX1_SLOT_MASK                0x003F  /* AIF3RX1_SLOT - [5:0] */
2964 #define WM5100_AIF3RX1_SLOT_SHIFT                    0  /* AIF3RX1_SLOT - [5:0] */
2965 #define WM5100_AIF3RX1_SLOT_WIDTH                    6  /* AIF3RX1_SLOT - [5:0] */
2968  * R1426 (0x592) - Audio IF 3_19
2970 #define WM5100_AIF3RX2_SLOT_MASK                0x003F  /* AIF3RX2_SLOT - [5:0] */
2971 #define WM5100_AIF3RX2_SLOT_SHIFT                    0  /* AIF3RX2_SLOT - [5:0] */
2972 #define WM5100_AIF3RX2_SLOT_WIDTH                    6  /* AIF3RX2_SLOT - [5:0] */
2975  * R1433 (0x599) - Audio IF 3_26
2979 #define WM5100_AIF3TX2_ENA_SHIFT                     1  /* AIF3TX2_ENA */
2980 #define WM5100_AIF3TX2_ENA_WIDTH                     1  /* AIF3TX2_ENA */
2984 #define WM5100_AIF3TX1_ENA_WIDTH                     1  /* AIF3TX1_ENA */
2987  * R1434 (0x59A) - Audio IF 3_27
2991 #define WM5100_AIF3RX2_ENA_SHIFT                     1  /* AIF3RX2_ENA */
2992 #define WM5100_AIF3RX2_ENA_WIDTH                     1  /* AIF3RX2_ENA */
2996 #define WM5100_AIF3RX1_ENA_WIDTH                     1  /* AIF3RX1_ENA */
2998 #define WM5100_MIXER_VOL_MASK                0x00FE  /* MIXER_VOL - [7:1] */
2999 #define WM5100_MIXER_VOL_SHIFT                    1  /* MIXER_VOL - [7:1] */
3000 #define WM5100_MIXER_VOL_WIDTH                    7  /* MIXER_VOL - [7:1] */
3003  * R3072 (0xC00) - GPIO CTRL 1
3007 #define WM5100_GP1_DIR_SHIFT                        15  /* GP1_DIR */
3008 #define WM5100_GP1_DIR_WIDTH                         1  /* GP1_DIR */
3012 #define WM5100_GP1_PU_WIDTH                          1  /* GP1_PU */
3016 #define WM5100_GP1_PD_WIDTH                          1  /* GP1_PD */
3020 #define WM5100_GP1_POL_WIDTH                         1  /* GP1_POL */
3024 #define WM5100_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
3028 #define WM5100_GP1_DB_WIDTH                          1  /* GP1_DB */
3032 #define WM5100_GP1_LVL_WIDTH                         1  /* GP1_LVL */
3033 #define WM5100_GP1_FN_MASK                      0x003F  /* GP1_FN - [5:0] */
3034 #define WM5100_GP1_FN_SHIFT                          0  /* GP1_FN - [5:0] */
3035 #define WM5100_GP1_FN_WIDTH                          6  /* GP1_FN - [5:0] */
3038  * R3073 (0xC01) - GPIO CTRL 2
3042 #define WM5100_GP2_DIR_SHIFT                        15  /* GP2_DIR */
3043 #define WM5100_GP2_DIR_WIDTH                         1  /* GP2_DIR */
3047 #define WM5100_GP2_PU_WIDTH                          1  /* GP2_PU */
3051 #define WM5100_GP2_PD_WIDTH                          1  /* GP2_PD */
3055 #define WM5100_GP2_POL_WIDTH                         1  /* GP2_POL */
3059 #define WM5100_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
3063 #define WM5100_GP2_DB_WIDTH                          1  /* GP2_DB */
3067 #define WM5100_GP2_LVL_WIDTH                         1  /* GP2_LVL */
3068 #define WM5100_GP2_FN_MASK                      0x003F  /* GP2_FN - [5:0] */
3069 #define WM5100_GP2_FN_SHIFT                          0  /* GP2_FN - [5:0] */
3070 #define WM5100_GP2_FN_WIDTH                          6  /* GP2_FN - [5:0] */
3073  * R3074 (0xC02) - GPIO CTRL 3
3077 #define WM5100_GP3_DIR_SHIFT                        15  /* GP3_DIR */
3078 #define WM5100_GP3_DIR_WIDTH                         1  /* GP3_DIR */
3082 #define WM5100_GP3_PU_WIDTH                          1  /* GP3_PU */
3086 #define WM5100_GP3_PD_WIDTH                          1  /* GP3_PD */
3090 #define WM5100_GP3_POL_WIDTH                         1  /* GP3_POL */
3094 #define WM5100_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
3098 #define WM5100_GP3_DB_WIDTH                          1  /* GP3_DB */
3102 #define WM5100_GP3_LVL_WIDTH                         1  /* GP3_LVL */
3103 #define WM5100_GP3_FN_MASK                      0x003F  /* GP3_FN - [5:0] */
3104 #define WM5100_GP3_FN_SHIFT                          0  /* GP3_FN - [5:0] */
3105 #define WM5100_GP3_FN_WIDTH                          6  /* GP3_FN - [5:0] */
3108  * R3075 (0xC03) - GPIO CTRL 4
3112 #define WM5100_GP4_DIR_SHIFT                        15  /* GP4_DIR */
3113 #define WM5100_GP4_DIR_WIDTH                         1  /* GP4_DIR */
3117 #define WM5100_GP4_PU_WIDTH                          1  /* GP4_PU */
3121 #define WM5100_GP4_PD_WIDTH                          1  /* GP4_PD */
3125 #define WM5100_GP4_POL_WIDTH                         1  /* GP4_POL */
3129 #define WM5100_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
3133 #define WM5100_GP4_DB_WIDTH                          1  /* GP4_DB */
3137 #define WM5100_GP4_LVL_WIDTH                         1  /* GP4_LVL */
3138 #define WM5100_GP4_FN_MASK                      0x003F  /* GP4_FN - [5:0] */
3139 #define WM5100_GP4_FN_SHIFT                          0  /* GP4_FN - [5:0] */
3140 #define WM5100_GP4_FN_WIDTH                          6  /* GP4_FN - [5:0] */
3143  * R3076 (0xC04) - GPIO CTRL 5
3147 #define WM5100_GP5_DIR_SHIFT                        15  /* GP5_DIR */
3148 #define WM5100_GP5_DIR_WIDTH                         1  /* GP5_DIR */
3152 #define WM5100_GP5_PU_WIDTH                          1  /* GP5_PU */
3156 #define WM5100_GP5_PD_WIDTH                          1  /* GP5_PD */
3160 #define WM5100_GP5_POL_WIDTH                         1  /* GP5_POL */
3164 #define WM5100_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
3168 #define WM5100_GP5_DB_WIDTH                          1  /* GP5_DB */
3172 #define WM5100_GP5_LVL_WIDTH                         1  /* GP5_LVL */
3173 #define WM5100_GP5_FN_MASK                      0x003F  /* GP5_FN - [5:0] */
3174 #define WM5100_GP5_FN_SHIFT                          0  /* GP5_FN - [5:0] */
3175 #define WM5100_GP5_FN_WIDTH                          6  /* GP5_FN - [5:0] */
3178  * R3077 (0xC05) - GPIO CTRL 6
3182 #define WM5100_GP6_DIR_SHIFT                        15  /* GP6_DIR */
3183 #define WM5100_GP6_DIR_WIDTH                         1  /* GP6_DIR */
3187 #define WM5100_GP6_PU_WIDTH                          1  /* GP6_PU */
3191 #define WM5100_GP6_PD_WIDTH                          1  /* GP6_PD */
3195 #define WM5100_GP6_POL_WIDTH                         1  /* GP6_POL */
3199 #define WM5100_GP6_OP_CFG_WIDTH                      1  /* GP6_OP_CFG */
3203 #define WM5100_GP6_DB_WIDTH                          1  /* GP6_DB */
3207 #define WM5100_GP6_LVL_WIDTH                         1  /* GP6_LVL */
3208 #define WM5100_GP6_FN_MASK                      0x003F  /* GP6_FN - [5:0] */
3209 #define WM5100_GP6_FN_SHIFT                          0  /* GP6_FN - [5:0] */
3210 #define WM5100_GP6_FN_WIDTH                          6  /* GP6_FN - [5:0] */
3213  * R3107 (0xC23) - Misc Pad Ctrl 1
3217 #define WM5100_LDO1ENA_PD_SHIFT                     15  /* LDO1ENA_PD */
3218 #define WM5100_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
3222 #define WM5100_MCLK2_PD_WIDTH                        1  /* MCLK2_PD */
3226 #define WM5100_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
3229 #define WM5100_RESET_PU_SHIFT                        1  /* RESET_PU */
3230 #define WM5100_RESET_PU_WIDTH                        1  /* RESET_PU */
3234 #define WM5100_ADDR_PD_WIDTH                         1  /* ADDR_PD */
3237  * R3108 (0xC24) - Misc Pad Ctrl 2
3242 #define WM5100_DMICDAT4_PD_WIDTH                     1  /* DMICDAT4_PD */
3246 #define WM5100_DMICDAT3_PD_WIDTH                     1  /* DMICDAT3_PD */
3249 #define WM5100_DMICDAT2_PD_SHIFT                     1  /* DMICDAT2_PD */
3250 #define WM5100_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
3254 #define WM5100_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
3257  * R3109 (0xC25) - Misc Pad Ctrl 3
3262 #define WM5100_AIF1RXLRCLK_PU_WIDTH                  1  /* AIF1RXLRCLK_PU */
3266 #define WM5100_AIF1RXLRCLK_PD_WIDTH                  1  /* AIF1RXLRCLK_PD */
3270 #define WM5100_AIF1BCLK_PU_WIDTH                     1  /* AIF1BCLK_PU */
3274 #define WM5100_AIF1BCLK_PD_WIDTH                     1  /* AIF1BCLK_PD */
3277 #define WM5100_AIF1RXDAT_PU_SHIFT                    1  /* AIF1RXDAT_PU */
3278 #define WM5100_AIF1RXDAT_PU_WIDTH                    1  /* AIF1RXDAT_PU */
3282 #define WM5100_AIF1RXDAT_PD_WIDTH                    1  /* AIF1RXDAT_PD */
3285  * R3110 (0xC26) - Misc Pad Ctrl 4
3290 #define WM5100_AIF2RXLRCLK_PU_WIDTH                  1  /* AIF2RXLRCLK_PU */
3294 #define WM5100_AIF2RXLRCLK_PD_WIDTH                  1  /* AIF2RXLRCLK_PD */
3298 #define WM5100_AIF2BCLK_PU_WIDTH                     1  /* AIF2BCLK_PU */
3302 #define WM5100_AIF2BCLK_PD_WIDTH                     1  /* AIF2BCLK_PD */
3305 #define WM5100_AIF2RXDAT_PU_SHIFT                    1  /* AIF2RXDAT_PU */
3306 #define WM5100_AIF2RXDAT_PU_WIDTH                    1  /* AIF2RXDAT_PU */
3310 #define WM5100_AIF2RXDAT_PD_WIDTH                    1  /* AIF2RXDAT_PD */
3313  * R3111 (0xC27) - Misc Pad Ctrl 5
3318 #define WM5100_AIF3RXLRCLK_PU_WIDTH                  1  /* AIF3RXLRCLK_PU */
3322 #define WM5100_AIF3RXLRCLK_PD_WIDTH                  1  /* AIF3RXLRCLK_PD */
3326 #define WM5100_AIF3BCLK_PU_WIDTH                     1  /* AIF3BCLK_PU */
3330 #define WM5100_AIF3BCLK_PD_WIDTH                     1  /* AIF3BCLK_PD */
3333 #define WM5100_AIF3RXDAT_PU_SHIFT                    1  /* AIF3RXDAT_PU */
3334 #define WM5100_AIF3RXDAT_PU_WIDTH                    1  /* AIF3RXDAT_PU */
3338 #define WM5100_AIF3RXDAT_PD_WIDTH                    1  /* AIF3RXDAT_PD */
3341  * R3112 (0xC28) - Misc GPIO 1
3343 #define WM5100_OPCLK_SEL_MASK                   0x0003  /* OPCLK_SEL - [1:0] */
3344 #define WM5100_OPCLK_SEL_SHIFT                       0  /* OPCLK_SEL - [1:0] */
3345 #define WM5100_OPCLK_SEL_WIDTH                       2  /* OPCLK_SEL - [1:0] */
3348  * R3328 (0xD00) - Interrupt Status 1
3353 #define WM5100_GP6_EINT_WIDTH                        1  /* GP6_EINT */
3357 #define WM5100_GP5_EINT_WIDTH                        1  /* GP5_EINT */
3361 #define WM5100_GP4_EINT_WIDTH                        1  /* GP4_EINT */
3365 #define WM5100_GP3_EINT_WIDTH                        1  /* GP3_EINT */
3368 #define WM5100_GP2_EINT_SHIFT                        1  /* GP2_EINT */
3369 #define WM5100_GP2_EINT_WIDTH                        1  /* GP2_EINT */
3373 #define WM5100_GP1_EINT_WIDTH                        1  /* GP1_EINT */
3376  * R3329 (0xD01) - Interrupt Status 2
3381 #define WM5100_DSP_IRQ6_EINT_WIDTH                   1  /* DSP_IRQ6_EINT */
3385 #define WM5100_DSP_IRQ5_EINT_WIDTH                   1  /* DSP_IRQ5_EINT */
3389 #define WM5100_DSP_IRQ4_EINT_WIDTH                   1  /* DSP_IRQ4_EINT */
3393 #define WM5100_DSP_IRQ3_EINT_WIDTH                   1  /* DSP_IRQ3_EINT */
3396 #define WM5100_DSP_IRQ2_EINT_SHIFT                   1  /* DSP_IRQ2_EINT */
3397 #define WM5100_DSP_IRQ2_EINT_WIDTH                   1  /* DSP_IRQ2_EINT */
3401 #define WM5100_DSP_IRQ1_EINT_WIDTH                   1  /* DSP_IRQ1_EINT */
3404  * R3330 (0xD02) - Interrupt Status 3
3408 #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT         15  /* SPK_SHUTDOWN_WARN_EINT */
3409 #define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH          1  /* SPK_SHUTDOWN_WARN_EINT */
3413 #define WM5100_SPK_SHUTDOWN_EINT_WIDTH               1  /* SPK_SHUTDOWN_EINT */
3417 #define WM5100_HPDET_EINT_WIDTH                      1  /* HPDET_EINT */
3421 #define WM5100_ACCDET_EINT_WIDTH                     1  /* ACCDET_EINT */
3425 #define WM5100_DRC_SIG_DET_EINT_WIDTH                1  /* DRC_SIG_DET_EINT */
3429 #define WM5100_ASRC2_LOCK_EINT_WIDTH                 1  /* ASRC2_LOCK_EINT */
3433 #define WM5100_ASRC1_LOCK_EINT_WIDTH                 1  /* ASRC1_LOCK_EINT */
3437 #define WM5100_FLL2_LOCK_EINT_WIDTH                  1  /* FLL2_LOCK_EINT */
3441 #define WM5100_FLL1_LOCK_EINT_WIDTH                  1  /* FLL1_LOCK_EINT */
3444 #define WM5100_CLKGEN_ERR_EINT_SHIFT                 1  /* CLKGEN_ERR_EINT */
3445 #define WM5100_CLKGEN_ERR_EINT_WIDTH                 1  /* CLKGEN_ERR_EINT */
3449 #define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH           1  /* CLKGEN_ERR_ASYNC_EINT */
3452  * R3331 (0xD03) - Interrupt Status 4
3457 #define WM5100_AIF3_ERR_EINT_WIDTH                   1  /* AIF3_ERR_EINT */
3461 #define WM5100_AIF2_ERR_EINT_WIDTH                   1  /* AIF2_ERR_EINT */
3465 #define WM5100_AIF1_ERR_EINT_WIDTH                   1  /* AIF1_ERR_EINT */
3469 #define WM5100_CTRLIF_ERR_EINT_WIDTH                 1  /* CTRLIF_ERR_EINT */
3473 #define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH         1  /* ISRC2_UNDERCLOCKED_EINT */
3477 #define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH         1  /* ISRC1_UNDERCLOCKED_EINT */
3481 #define WM5100_FX_UNDERCLOCKED_EINT_WIDTH            1  /* FX_UNDERCLOCKED_EINT */
3485 #define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH          1  /* AIF3_UNDERCLOCKED_EINT */
3489 #define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH          1  /* AIF2_UNDERCLOCKED_EINT */
3493 #define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH          1  /* AIF1_UNDERCLOCKED_EINT */
3497 #define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH          1  /* ASRC_UNDERCLOCKED_EINT */
3501 #define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH           1  /* DAC_UNDERCLOCKED_EINT */
3504 #define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT           1  /* ADC_UNDERCLOCKED_EINT */
3505 #define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH           1  /* ADC_UNDERCLOCKED_EINT */
3509 #define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH         1  /* MIXER_UNDERCLOCKED_EINT */
3512  * R3332 (0xD04) - Interrupt Raw Status 2
3517 #define WM5100_DSP_IRQ6_STS_WIDTH                    1  /* DSP_IRQ6_STS */
3521 #define WM5100_DSP_IRQ5_STS_WIDTH                    1  /* DSP_IRQ5_STS */
3525 #define WM5100_DSP_IRQ4_STS_WIDTH                    1  /* DSP_IRQ4_STS */
3529 #define WM5100_DSP_IRQ3_STS_WIDTH                    1  /* DSP_IRQ3_STS */
3532 #define WM5100_DSP_IRQ2_STS_SHIFT                    1  /* DSP_IRQ2_STS */
3533 #define WM5100_DSP_IRQ2_STS_WIDTH                    1  /* DSP_IRQ2_STS */
3537 #define WM5100_DSP_IRQ1_STS_WIDTH                    1  /* DSP_IRQ1_STS */
3540  * R3333 (0xD05) - Interrupt Raw Status 3
3544 #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT          15  /* SPK_SHUTDOWN_WARN_STS */
3545 #define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH           1  /* SPK_SHUTDOWN_WARN_STS */
3549 #define WM5100_SPK_SHUTDOWN_STS_WIDTH                1  /* SPK_SHUTDOWN_STS */
3553 #define WM5100_HPDET_STS_WIDTH                       1  /* HPDET_STS */
3557 #define WM5100_DRC_SID_DET_STS_WIDTH                 1  /* DRC_SID_DET_STS */
3561 #define WM5100_ASRC2_LOCK_STS_WIDTH                  1  /* ASRC2_LOCK_STS */
3565 #define WM5100_ASRC1_LOCK_STS_WIDTH                  1  /* ASRC1_LOCK_STS */
3569 #define WM5100_FLL2_LOCK_STS_WIDTH                   1  /* FLL2_LOCK_STS */
3573 #define WM5100_FLL1_LOCK_STS_WIDTH                   1  /* FLL1_LOCK_STS */
3576 #define WM5100_CLKGEN_ERR_STS_SHIFT                  1  /* CLKGEN_ERR_STS */
3577 #define WM5100_CLKGEN_ERR_STS_WIDTH                  1  /* CLKGEN_ERR_STS */
3581 #define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH            1  /* CLKGEN_ERR_ASYNC_STS */
3584  * R3334 (0xD06) - Interrupt Raw Status 4
3589 #define WM5100_AIF3_ERR_STS_WIDTH                    1  /* AIF3_ERR_STS */
3593 #define WM5100_AIF2_ERR_STS_WIDTH                    1  /* AIF2_ERR_STS */
3597 #define WM5100_AIF1_ERR_STS_WIDTH                    1  /* AIF1_ERR_STS */
3601 #define WM5100_CTRLIF_ERR_STS_WIDTH                  1  /* CTRLIF_ERR_STS */
3605 #define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH          1  /* ISRC2_UNDERCLOCKED_STS */
3609 #define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH          1  /* ISRC1_UNDERCLOCKED_STS */
3613 #define WM5100_FX_UNDERCLOCKED_STS_WIDTH             1  /* FX_UNDERCLOCKED_STS */
3617 #define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH           1  /* AIF3_UNDERCLOCKED_STS */
3621 #define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH           1  /* AIF2_UNDERCLOCKED_STS */
3625 #define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH           1  /* AIF1_UNDERCLOCKED_STS */
3629 #define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH           1  /* ASRC_UNDERCLOCKED_STS */
3633 #define WM5100_DAC_UNDERCLOCKED_STS_WIDTH            1  /* DAC_UNDERCLOCKED_STS */
3636 #define WM5100_ADC_UNDERCLOCKED_STS_SHIFT            1  /* ADC_UNDERCLOCKED_STS */
3637 #define WM5100_ADC_UNDERCLOCKED_STS_WIDTH            1  /* ADC_UNDERCLOCKED_STS */
3641 #define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH          1  /* MIXER_UNDERCLOCKED_STS */
3644  * R3335 (0xD07) - Interrupt Status 1 Mask
3649 #define WM5100_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
3653 #define WM5100_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
3657 #define WM5100_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
3661 #define WM5100_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
3664 #define WM5100_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
3665 #define WM5100_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
3669 #define WM5100_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
3672  * R3336 (0xD08) - Interrupt Status 2 Mask
3677 #define WM5100_IM_DSP_IRQ6_EINT_WIDTH                1  /* IM_DSP_IRQ6_EINT */
3681 #define WM5100_IM_DSP_IRQ5_EINT_WIDTH                1  /* IM_DSP_IRQ5_EINT */
3685 #define WM5100_IM_DSP_IRQ4_EINT_WIDTH                1  /* IM_DSP_IRQ4_EINT */
3689 #define WM5100_IM_DSP_IRQ3_EINT_WIDTH                1  /* IM_DSP_IRQ3_EINT */
3692 #define WM5100_IM_DSP_IRQ2_EINT_SHIFT                1  /* IM_DSP_IRQ2_EINT */
3693 #define WM5100_IM_DSP_IRQ2_EINT_WIDTH                1  /* IM_DSP_IRQ2_EINT */
3697 #define WM5100_IM_DSP_IRQ1_EINT_WIDTH                1  /* IM_DSP_IRQ1_EINT */
3700  * R3337 (0xD09) - Interrupt Status 3 Mask
3704 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT      15  /* IM_SPK_SHUTDOWN_WARN_EINT */
3705 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH       1  /* IM_SPK_SHUTDOWN_WARN_EINT */
3709 #define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH            1  /* IM_SPK_SHUTDOWN_EINT */
3713 #define WM5100_IM_HPDET_EINT_WIDTH                   1  /* IM_HPDET_EINT */
3717 #define WM5100_IM_ACCDET_EINT_WIDTH                  1  /* IM_ACCDET_EINT */
3721 #define WM5100_IM_DRC_SIG_DET_EINT_WIDTH             1  /* IM_DRC_SIG_DET_EINT */
3725 #define WM5100_IM_ASRC2_LOCK_EINT_WIDTH              1  /* IM_ASRC2_LOCK_EINT */
3729 #define WM5100_IM_ASRC1_LOCK_EINT_WIDTH              1  /* IM_ASRC1_LOCK_EINT */
3733 #define WM5100_IM_FLL2_LOCK_EINT_WIDTH               1  /* IM_FLL2_LOCK_EINT */
3737 #define WM5100_IM_FLL1_LOCK_EINT_WIDTH               1  /* IM_FLL1_LOCK_EINT */
3740 #define WM5100_IM_CLKGEN_ERR_EINT_SHIFT              1  /* IM_CLKGEN_ERR_EINT */
3741 #define WM5100_IM_CLKGEN_ERR_EINT_WIDTH              1  /* IM_CLKGEN_ERR_EINT */
3745 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH        1  /* IM_CLKGEN_ERR_ASYNC_EINT */
3748  * R3338 (0xD0A) - Interrupt Status 4 Mask
3753 #define WM5100_IM_AIF3_ERR_EINT_WIDTH                1  /* IM_AIF3_ERR_EINT */
3757 #define WM5100_IM_AIF2_ERR_EINT_WIDTH                1  /* IM_AIF2_ERR_EINT */
3761 #define WM5100_IM_AIF1_ERR_EINT_WIDTH                1  /* IM_AIF1_ERR_EINT */
3765 #define WM5100_IM_CTRLIF_ERR_EINT_WIDTH              1  /* IM_CTRLIF_ERR_EINT */
3769 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH      1  /* IM_ISRC2_UNDERCLOCKED_EINT */
3773 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH      1  /* IM_ISRC1_UNDERCLOCKED_EINT */
3777 #define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH         1  /* IM_FX_UNDERCLOCKED_EINT */
3781 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH       1  /* IM_AIF3_UNDERCLOCKED_EINT */
3785 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH       1  /* IM_AIF2_UNDERCLOCKED_EINT */
3789 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH       1  /* IM_AIF1_UNDERCLOCKED_EINT */
3793 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH       1  /* IM_ASRC_UNDERCLOCKED_EINT */
3797 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH        1  /* IM_DAC_UNDERCLOCKED_EINT */
3800 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT        1  /* IM_ADC_UNDERCLOCKED_EINT */
3801 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH        1  /* IM_ADC_UNDERCLOCKED_EINT */
3805 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH      1  /* IM_MIXER_UNDERCLOCKED_EINT */
3808  * R3359 (0xD1F) - Interrupt Control
3813 #define WM5100_IM_IRQ_WIDTH                          1  /* IM_IRQ */
3816  * R3360 (0xD20) - IRQ Debounce 1
3821 #define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH            1  /* SPK_SHUTDOWN_WARN_DB */
3825 #define WM5100_SPK_SHUTDOWN_DB_WIDTH                 1  /* SPK_SHUTDOWN_DB */
3829 #define WM5100_FLL1_LOCK_IRQ_DB_WIDTH                1  /* FLL1_LOCK_IRQ_DB */
3833 #define WM5100_FLL2_LOCK_IRQ_DB_WIDTH                1  /* FLL2_LOCK_IRQ_DB */
3836 #define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT               1  /* CLKGEN_ERR_IRQ_DB */
3837 #define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH               1  /* CLKGEN_ERR_IRQ_DB */
3841 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH         1  /* CLKGEN_ERR_ASYNC_IRQ_DB */
3844  * R3361 (0xD21) - IRQ Debounce 2
3849 #define WM5100_AIF_ERR_DB_WIDTH                      1  /* AIF_ERR_DB */
3852  * R3584 (0xE00) - FX_Ctrl
3854 #define WM5100_FX_STS_MASK                      0xFFC0  /* FX_STS - [15:6] */
3855 #define WM5100_FX_STS_SHIFT                          6  /* FX_STS - [15:6] */
3856 #define WM5100_FX_STS_WIDTH                         10  /* FX_STS - [15:6] */
3857 #define WM5100_FX_RATE_MASK                     0x0003  /* FX_RATE - [1:0] */
3858 #define WM5100_FX_RATE_SHIFT                         0  /* FX_RATE - [1:0] */
3859 #define WM5100_FX_RATE_WIDTH                         2  /* FX_RATE - [1:0] */
3862  * R3600 (0xE10) - EQ1_1
3864 #define WM5100_EQ1_B1_GAIN_MASK                 0xF800  /* EQ1_B1_GAIN - [15:11] */
3865 #define WM5100_EQ1_B1_GAIN_SHIFT                    11  /* EQ1_B1_GAIN - [15:11] */
3866 #define WM5100_EQ1_B1_GAIN_WIDTH                     5  /* EQ1_B1_GAIN - [15:11] */
3867 #define WM5100_EQ1_B2_GAIN_MASK                 0x07C0  /* EQ1_B2_GAIN - [10:6] */
3868 #define WM5100_EQ1_B2_GAIN_SHIFT                     6  /* EQ1_B2_GAIN - [10:6] */
3869 #define WM5100_EQ1_B2_GAIN_WIDTH                     5  /* EQ1_B2_GAIN - [10:6] */
3870 #define WM5100_EQ1_B3_GAIN_MASK                 0x003E  /* EQ1_B3_GAIN - [5:1] */
3871 #define WM5100_EQ1_B3_GAIN_SHIFT                     1  /* EQ1_B3_GAIN - [5:1] */
3872 #define WM5100_EQ1_B3_GAIN_WIDTH                     5  /* EQ1_B3_GAIN - [5:1] */
3876 #define WM5100_EQ1_ENA_WIDTH                         1  /* EQ1_ENA */
3879  * R3601 (0xE11) - EQ1_2
3881 #define WM5100_EQ1_B4_GAIN_MASK                 0xF800  /* EQ1_B4_GAIN - [15:11] */
3882 #define WM5100_EQ1_B4_GAIN_SHIFT                    11  /* EQ1_B4_GAIN - [15:11] */
3883 #define WM5100_EQ1_B4_GAIN_WIDTH                     5  /* EQ1_B4_GAIN - [15:11] */
3884 #define WM5100_EQ1_B5_GAIN_MASK                 0x07C0  /* EQ1_B5_GAIN - [10:6] */
3885 #define WM5100_EQ1_B5_GAIN_SHIFT                     6  /* EQ1_B5_GAIN - [10:6] */
3886 #define WM5100_EQ1_B5_GAIN_WIDTH                     5  /* EQ1_B5_GAIN - [10:6] */
3889  * R3602 (0xE12) - EQ1_3
3891 #define WM5100_EQ1_B1_A_MASK                    0xFFFF  /* EQ1_B1_A - [15:0] */
3892 #define WM5100_EQ1_B1_A_SHIFT                        0  /* EQ1_B1_A - [15:0] */
3893 #define WM5100_EQ1_B1_A_WIDTH                       16  /* EQ1_B1_A - [15:0] */
3896  * R3603 (0xE13) - EQ1_4
3898 #define WM5100_EQ1_B1_B_MASK                    0xFFFF  /* EQ1_B1_B - [15:0] */
3899 #define WM5100_EQ1_B1_B_SHIFT                        0  /* EQ1_B1_B - [15:0] */
3900 #define WM5100_EQ1_B1_B_WIDTH                       16  /* EQ1_B1_B - [15:0] */
3903  * R3604 (0xE14) - EQ1_5
3905 #define WM5100_EQ1_B1_PG_MASK                   0xFFFF  /* EQ1_B1_PG - [15:0] */
3906 #define WM5100_EQ1_B1_PG_SHIFT                       0  /* EQ1_B1_PG - [15:0] */
3907 #define WM5100_EQ1_B1_PG_WIDTH                      16  /* EQ1_B1_PG - [15:0] */
3910  * R3605 (0xE15) - EQ1_6
3912 #define WM5100_EQ1_B2_A_MASK                    0xFFFF  /* EQ1_B2_A - [15:0] */
3913 #define WM5100_EQ1_B2_A_SHIFT                        0  /* EQ1_B2_A - [15:0] */
3914 #define WM5100_EQ1_B2_A_WIDTH                       16  /* EQ1_B2_A - [15:0] */
3917  * R3606 (0xE16) - EQ1_7
3919 #define WM5100_EQ1_B2_B_MASK                    0xFFFF  /* EQ1_B2_B - [15:0] */
3920 #define WM5100_EQ1_B2_B_SHIFT                        0  /* EQ1_B2_B - [15:0] */
3921 #define WM5100_EQ1_B2_B_WIDTH                       16  /* EQ1_B2_B - [15:0] */
3924  * R3607 (0xE17) - EQ1_8
3926 #define WM5100_EQ1_B2_C_MASK                    0xFFFF  /* EQ1_B2_C - [15:0] */
3927 #define WM5100_EQ1_B2_C_SHIFT                        0  /* EQ1_B2_C - [15:0] */
3928 #define WM5100_EQ1_B2_C_WIDTH                       16  /* EQ1_B2_C - [15:0] */
3931  * R3608 (0xE18) - EQ1_9
3933 #define WM5100_EQ1_B2_PG_MASK                   0xFFFF  /* EQ1_B2_PG - [15:0] */
3934 #define WM5100_EQ1_B2_PG_SHIFT                       0  /* EQ1_B2_PG - [15:0] */
3935 #define WM5100_EQ1_B2_PG_WIDTH                      16  /* EQ1_B2_PG - [15:0] */
3938  * R3609 (0xE19) - EQ1_10
3940 #define WM5100_EQ1_B3_A_MASK                    0xFFFF  /* EQ1_B3_A - [15:0] */
3941 #define WM5100_EQ1_B3_A_SHIFT                        0  /* EQ1_B3_A - [15:0] */
3942 #define WM5100_EQ1_B3_A_WIDTH                       16  /* EQ1_B3_A - [15:0] */
3945  * R3610 (0xE1A) - EQ1_11
3947 #define WM5100_EQ1_B3_B_MASK                    0xFFFF  /* EQ1_B3_B - [15:0] */
3948 #define WM5100_EQ1_B3_B_SHIFT                        0  /* EQ1_B3_B - [15:0] */
3949 #define WM5100_EQ1_B3_B_WIDTH                       16  /* EQ1_B3_B - [15:0] */
3952  * R3611 (0xE1B) - EQ1_12
3954 #define WM5100_EQ1_B3_C_MASK                    0xFFFF  /* EQ1_B3_C - [15:0] */
3955 #define WM5100_EQ1_B3_C_SHIFT                        0  /* EQ1_B3_C - [15:0] */
3956 #define WM5100_EQ1_B3_C_WIDTH                       16  /* EQ1_B3_C - [15:0] */
3959  * R3612 (0xE1C) - EQ1_13
3961 #define WM5100_EQ1_B3_PG_MASK                   0xFFFF  /* EQ1_B3_PG - [15:0] */
3962 #define WM5100_EQ1_B3_PG_SHIFT                       0  /* EQ1_B3_PG - [15:0] */
3963 #define WM5100_EQ1_B3_PG_WIDTH                      16  /* EQ1_B3_PG - [15:0] */
3966  * R3613 (0xE1D) - EQ1_14
3968 #define WM5100_EQ1_B4_A_MASK                    0xFFFF  /* EQ1_B4_A - [15:0] */
3969 #define WM5100_EQ1_B4_A_SHIFT                        0  /* EQ1_B4_A - [15:0] */
3970 #define WM5100_EQ1_B4_A_WIDTH                       16  /* EQ1_B4_A - [15:0] */
3973  * R3614 (0xE1E) - EQ1_15
3975 #define WM5100_EQ1_B4_B_MASK                    0xFFFF  /* EQ1_B4_B - [15:0] */
3976 #define WM5100_EQ1_B4_B_SHIFT                        0  /* EQ1_B4_B - [15:0] */
3977 #define WM5100_EQ1_B4_B_WIDTH                       16  /* EQ1_B4_B - [15:0] */
3980  * R3615 (0xE1F) - EQ1_16
3982 #define WM5100_EQ1_B4_C_MASK                    0xFFFF  /* EQ1_B4_C - [15:0] */
3983 #define WM5100_EQ1_B4_C_SHIFT                        0  /* EQ1_B4_C - [15:0] */
3984 #define WM5100_EQ1_B4_C_WIDTH                       16  /* EQ1_B4_C - [15:0] */
3987  * R3616 (0xE20) - EQ1_17
3989 #define WM5100_EQ1_B4_PG_MASK                   0xFFFF  /* EQ1_B4_PG - [15:0] */
3990 #define WM5100_EQ1_B4_PG_SHIFT                       0  /* EQ1_B4_PG - [15:0] */
3991 #define WM5100_EQ1_B4_PG_WIDTH                      16  /* EQ1_B4_PG - [15:0] */
3994  * R3617 (0xE21) - EQ1_18
3996 #define WM5100_EQ1_B5_A_MASK                    0xFFFF  /* EQ1_B5_A - [15:0] */
3997 #define WM5100_EQ1_B5_A_SHIFT                        0  /* EQ1_B5_A - [15:0] */
3998 #define WM5100_EQ1_B5_A_WIDTH                       16  /* EQ1_B5_A - [15:0] */
4001  * R3618 (0xE22) - EQ1_19
4003 #define WM5100_EQ1_B5_B_MASK                    0xFFFF  /* EQ1_B5_B - [15:0] */
4004 #define WM5100_EQ1_B5_B_SHIFT                        0  /* EQ1_B5_B - [15:0] */
4005 #define WM5100_EQ1_B5_B_WIDTH                       16  /* EQ1_B5_B - [15:0] */
4008  * R3619 (0xE23) - EQ1_20
4010 #define WM5100_EQ1_B5_PG_MASK                   0xFFFF  /* EQ1_B5_PG - [15:0] */
4011 #define WM5100_EQ1_B5_PG_SHIFT                       0  /* EQ1_B5_PG - [15:0] */
4012 #define WM5100_EQ1_B5_PG_WIDTH                      16  /* EQ1_B5_PG - [15:0] */
4015  * R3622 (0xE26) - EQ2_1
4017 #define WM5100_EQ2_B1_GAIN_MASK                 0xF800  /* EQ2_B1_GAIN - [15:11] */
4018 #define WM5100_EQ2_B1_GAIN_SHIFT                    11  /* EQ2_B1_GAIN - [15:11] */
4019 #define WM5100_EQ2_B1_GAIN_WIDTH                     5  /* EQ2_B1_GAIN - [15:11] */
4020 #define WM5100_EQ2_B2_GAIN_MASK                 0x07C0  /* EQ2_B2_GAIN - [10:6] */
4021 #define WM5100_EQ2_B2_GAIN_SHIFT                     6  /* EQ2_B2_GAIN - [10:6] */
4022 #define WM5100_EQ2_B2_GAIN_WIDTH                     5  /* EQ2_B2_GAIN - [10:6] */
4023 #define WM5100_EQ2_B3_GAIN_MASK                 0x003E  /* EQ2_B3_GAIN - [5:1] */
4024 #define WM5100_EQ2_B3_GAIN_SHIFT                     1  /* EQ2_B3_GAIN - [5:1] */
4025 #define WM5100_EQ2_B3_GAIN_WIDTH                     5  /* EQ2_B3_GAIN - [5:1] */
4029 #define WM5100_EQ2_ENA_WIDTH                         1  /* EQ2_ENA */
4032  * R3623 (0xE27) - EQ2_2
4034 #define WM5100_EQ2_B4_GAIN_MASK                 0xF800  /* EQ2_B4_GAIN - [15:11] */
4035 #define WM5100_EQ2_B4_GAIN_SHIFT                    11  /* EQ2_B4_GAIN - [15:11] */
4036 #define WM5100_EQ2_B4_GAIN_WIDTH                     5  /* EQ2_B4_GAIN - [15:11] */
4037 #define WM5100_EQ2_B5_GAIN_MASK                 0x07C0  /* EQ2_B5_GAIN - [10:6] */
4038 #define WM5100_EQ2_B5_GAIN_SHIFT                     6  /* EQ2_B5_GAIN - [10:6] */
4039 #define WM5100_EQ2_B5_GAIN_WIDTH                     5  /* EQ2_B5_GAIN - [10:6] */
4042  * R3624 (0xE28) - EQ2_3
4044 #define WM5100_EQ2_B1_A_MASK                    0xFFFF  /* EQ2_B1_A - [15:0] */
4045 #define WM5100_EQ2_B1_A_SHIFT                        0  /* EQ2_B1_A - [15:0] */
4046 #define WM5100_EQ2_B1_A_WIDTH                       16  /* EQ2_B1_A - [15:0] */
4049  * R3625 (0xE29) - EQ2_4
4051 #define WM5100_EQ2_B1_B_MASK                    0xFFFF  /* EQ2_B1_B - [15:0] */
4052 #define WM5100_EQ2_B1_B_SHIFT                        0  /* EQ2_B1_B - [15:0] */
4053 #define WM5100_EQ2_B1_B_WIDTH                       16  /* EQ2_B1_B - [15:0] */
4056  * R3626 (0xE2A) - EQ2_5
4058 #define WM5100_EQ2_B1_PG_MASK                   0xFFFF  /* EQ2_B1_PG - [15:0] */
4059 #define WM5100_EQ2_B1_PG_SHIFT                       0  /* EQ2_B1_PG - [15:0] */
4060 #define WM5100_EQ2_B1_PG_WIDTH                      16  /* EQ2_B1_PG - [15:0] */
4063  * R3627 (0xE2B) - EQ2_6
4065 #define WM5100_EQ2_B2_A_MASK                    0xFFFF  /* EQ2_B2_A - [15:0] */
4066 #define WM5100_EQ2_B2_A_SHIFT                        0  /* EQ2_B2_A - [15:0] */
4067 #define WM5100_EQ2_B2_A_WIDTH                       16  /* EQ2_B2_A - [15:0] */
4070  * R3628 (0xE2C) - EQ2_7
4072 #define WM5100_EQ2_B2_B_MASK                    0xFFFF  /* EQ2_B2_B - [15:0] */
4073 #define WM5100_EQ2_B2_B_SHIFT                        0  /* EQ2_B2_B - [15:0] */
4074 #define WM5100_EQ2_B2_B_WIDTH                       16  /* EQ2_B2_B - [15:0] */
4077  * R3629 (0xE2D) - EQ2_8
4079 #define WM5100_EQ2_B2_C_MASK                    0xFFFF  /* EQ2_B2_C - [15:0] */
4080 #define WM5100_EQ2_B2_C_SHIFT                        0  /* EQ2_B2_C - [15:0] */
4081 #define WM5100_EQ2_B2_C_WIDTH                       16  /* EQ2_B2_C - [15:0] */
4084  * R3630 (0xE2E) - EQ2_9
4086 #define WM5100_EQ2_B2_PG_MASK                   0xFFFF  /* EQ2_B2_PG - [15:0] */
4087 #define WM5100_EQ2_B2_PG_SHIFT                       0  /* EQ2_B2_PG - [15:0] */
4088 #define WM5100_EQ2_B2_PG_WIDTH                      16  /* EQ2_B2_PG - [15:0] */
4091  * R3631 (0xE2F) - EQ2_10
4093 #define WM5100_EQ2_B3_A_MASK                    0xFFFF  /* EQ2_B3_A - [15:0] */
4094 #define WM5100_EQ2_B3_A_SHIFT                        0  /* EQ2_B3_A - [15:0] */
4095 #define WM5100_EQ2_B3_A_WIDTH                       16  /* EQ2_B3_A - [15:0] */
4098  * R3632 (0xE30) - EQ2_11
4100 #define WM5100_EQ2_B3_B_MASK                    0xFFFF  /* EQ2_B3_B - [15:0] */
4101 #define WM5100_EQ2_B3_B_SHIFT                        0  /* EQ2_B3_B - [15:0] */
4102 #define WM5100_EQ2_B3_B_WIDTH                       16  /* EQ2_B3_B - [15:0] */
4105  * R3633 (0xE31) - EQ2_12
4107 #define WM5100_EQ2_B3_C_MASK                    0xFFFF  /* EQ2_B3_C - [15:0] */
4108 #define WM5100_EQ2_B3_C_SHIFT                        0  /* EQ2_B3_C - [15:0] */
4109 #define WM5100_EQ2_B3_C_WIDTH                       16  /* EQ2_B3_C - [15:0] */
4112  * R3634 (0xE32) - EQ2_13
4114 #define WM5100_EQ2_B3_PG_MASK                   0xFFFF  /* EQ2_B3_PG - [15:0] */
4115 #define WM5100_EQ2_B3_PG_SHIFT                       0  /* EQ2_B3_PG - [15:0] */
4116 #define WM5100_EQ2_B3_PG_WIDTH                      16  /* EQ2_B3_PG - [15:0] */
4119  * R3635 (0xE33) - EQ2_14
4121 #define WM5100_EQ2_B4_A_MASK                    0xFFFF  /* EQ2_B4_A - [15:0] */
4122 #define WM5100_EQ2_B4_A_SHIFT                        0  /* EQ2_B4_A - [15:0] */
4123 #define WM5100_EQ2_B4_A_WIDTH                       16  /* EQ2_B4_A - [15:0] */
4126  * R3636 (0xE34) - EQ2_15
4128 #define WM5100_EQ2_B4_B_MASK                    0xFFFF  /* EQ2_B4_B - [15:0] */
4129 #define WM5100_EQ2_B4_B_SHIFT                        0  /* EQ2_B4_B - [15:0] */
4130 #define WM5100_EQ2_B4_B_WIDTH                       16  /* EQ2_B4_B - [15:0] */
4133  * R3637 (0xE35) - EQ2_16
4135 #define WM5100_EQ2_B4_C_MASK                    0xFFFF  /* EQ2_B4_C - [15:0] */
4136 #define WM5100_EQ2_B4_C_SHIFT                        0  /* EQ2_B4_C - [15:0] */
4137 #define WM5100_EQ2_B4_C_WIDTH                       16  /* EQ2_B4_C - [15:0] */
4140  * R3638 (0xE36) - EQ2_17
4142 #define WM5100_EQ2_B4_PG_MASK                   0xFFFF  /* EQ2_B4_PG - [15:0] */
4143 #define WM5100_EQ2_B4_PG_SHIFT                       0  /* EQ2_B4_PG - [15:0] */
4144 #define WM5100_EQ2_B4_PG_WIDTH                      16  /* EQ2_B4_PG - [15:0] */
4147  * R3639 (0xE37) - EQ2_18
4149 #define WM5100_EQ2_B5_A_MASK                    0xFFFF  /* EQ2_B5_A - [15:0] */
4150 #define WM5100_EQ2_B5_A_SHIFT                        0  /* EQ2_B5_A - [15:0] */
4151 #define WM5100_EQ2_B5_A_WIDTH                       16  /* EQ2_B5_A - [15:0] */
4154  * R3640 (0xE38) - EQ2_19
4156 #define WM5100_EQ2_B5_B_MASK                    0xFFFF  /* EQ2_B5_B - [15:0] */
4157 #define WM5100_EQ2_B5_B_SHIFT                        0  /* EQ2_B5_B - [15:0] */
4158 #define WM5100_EQ2_B5_B_WIDTH                       16  /* EQ2_B5_B - [15:0] */
4161  * R3641 (0xE39) - EQ2_20
4163 #define WM5100_EQ2_B5_PG_MASK                   0xFFFF  /* EQ2_B5_PG - [15:0] */
4164 #define WM5100_EQ2_B5_PG_SHIFT                       0  /* EQ2_B5_PG - [15:0] */
4165 #define WM5100_EQ2_B5_PG_WIDTH                      16  /* EQ2_B5_PG - [15:0] */
4168  * R3644 (0xE3C) - EQ3_1
4170 #define WM5100_EQ3_B1_GAIN_MASK                 0xF800  /* EQ3_B1_GAIN - [15:11] */
4171 #define WM5100_EQ3_B1_GAIN_SHIFT                    11  /* EQ3_B1_GAIN - [15:11] */
4172 #define WM5100_EQ3_B1_GAIN_WIDTH                     5  /* EQ3_B1_GAIN - [15:11] */
4173 #define WM5100_EQ3_B2_GAIN_MASK                 0x07C0  /* EQ3_B2_GAIN - [10:6] */
4174 #define WM5100_EQ3_B2_GAIN_SHIFT                     6  /* EQ3_B2_GAIN - [10:6] */
4175 #define WM5100_EQ3_B2_GAIN_WIDTH                     5  /* EQ3_B2_GAIN - [10:6] */
4176 #define WM5100_EQ3_B3_GAIN_MASK                 0x003E  /* EQ3_B3_GAIN - [5:1] */
4177 #define WM5100_EQ3_B3_GAIN_SHIFT                     1  /* EQ3_B3_GAIN - [5:1] */
4178 #define WM5100_EQ3_B3_GAIN_WIDTH                     5  /* EQ3_B3_GAIN - [5:1] */
4182 #define WM5100_EQ3_ENA_WIDTH                         1  /* EQ3_ENA */
4185  * R3645 (0xE3D) - EQ3_2
4187 #define WM5100_EQ3_B4_GAIN_MASK                 0xF800  /* EQ3_B4_GAIN - [15:11] */
4188 #define WM5100_EQ3_B4_GAIN_SHIFT                    11  /* EQ3_B4_GAIN - [15:11] */
4189 #define WM5100_EQ3_B4_GAIN_WIDTH                     5  /* EQ3_B4_GAIN - [15:11] */
4190 #define WM5100_EQ3_B5_GAIN_MASK                 0x07C0  /* EQ3_B5_GAIN - [10:6] */
4191 #define WM5100_EQ3_B5_GAIN_SHIFT                     6  /* EQ3_B5_GAIN - [10:6] */
4192 #define WM5100_EQ3_B5_GAIN_WIDTH                     5  /* EQ3_B5_GAIN - [10:6] */
4195  * R3646 (0xE3E) - EQ3_3
4197 #define WM5100_EQ3_B1_A_MASK                    0xFFFF  /* EQ3_B1_A - [15:0] */
4198 #define WM5100_EQ3_B1_A_SHIFT                        0  /* EQ3_B1_A - [15:0] */
4199 #define WM5100_EQ3_B1_A_WIDTH                       16  /* EQ3_B1_A - [15:0] */
4202  * R3647 (0xE3F) - EQ3_4
4204 #define WM5100_EQ3_B1_B_MASK                    0xFFFF  /* EQ3_B1_B - [15:0] */
4205 #define WM5100_EQ3_B1_B_SHIFT                        0  /* EQ3_B1_B - [15:0] */
4206 #define WM5100_EQ3_B1_B_WIDTH                       16  /* EQ3_B1_B - [15:0] */
4209  * R3648 (0xE40) - EQ3_5
4211 #define WM5100_EQ3_B1_PG_MASK                   0xFFFF  /* EQ3_B1_PG - [15:0] */
4212 #define WM5100_EQ3_B1_PG_SHIFT                       0  /* EQ3_B1_PG - [15:0] */
4213 #define WM5100_EQ3_B1_PG_WIDTH                      16  /* EQ3_B1_PG - [15:0] */
4216  * R3649 (0xE41) - EQ3_6
4218 #define WM5100_EQ3_B2_A_MASK                    0xFFFF  /* EQ3_B2_A - [15:0] */
4219 #define WM5100_EQ3_B2_A_SHIFT                        0  /* EQ3_B2_A - [15:0] */
4220 #define WM5100_EQ3_B2_A_WIDTH                       16  /* EQ3_B2_A - [15:0] */
4223  * R3650 (0xE42) - EQ3_7
4225 #define WM5100_EQ3_B2_B_MASK                    0xFFFF  /* EQ3_B2_B - [15:0] */
4226 #define WM5100_EQ3_B2_B_SHIFT                        0  /* EQ3_B2_B - [15:0] */
4227 #define WM5100_EQ3_B2_B_WIDTH                       16  /* EQ3_B2_B - [15:0] */
4230  * R3651 (0xE43) - EQ3_8
4232 #define WM5100_EQ3_B2_C_MASK                    0xFFFF  /* EQ3_B2_C - [15:0] */
4233 #define WM5100_EQ3_B2_C_SHIFT                        0  /* EQ3_B2_C - [15:0] */
4234 #define WM5100_EQ3_B2_C_WIDTH                       16  /* EQ3_B2_C - [15:0] */
4237  * R3652 (0xE44) - EQ3_9
4239 #define WM5100_EQ3_B2_PG_MASK                   0xFFFF  /* EQ3_B2_PG - [15:0] */
4240 #define WM5100_EQ3_B2_PG_SHIFT                       0  /* EQ3_B2_PG - [15:0] */
4241 #define WM5100_EQ3_B2_PG_WIDTH                      16  /* EQ3_B2_PG - [15:0] */
4244  * R3653 (0xE45) - EQ3_10
4246 #define WM5100_EQ3_B3_A_MASK                    0xFFFF  /* EQ3_B3_A - [15:0] */
4247 #define WM5100_EQ3_B3_A_SHIFT                        0  /* EQ3_B3_A - [15:0] */
4248 #define WM5100_EQ3_B3_A_WIDTH                       16  /* EQ3_B3_A - [15:0] */
4251  * R3654 (0xE46) - EQ3_11
4253 #define WM5100_EQ3_B3_B_MASK                    0xFFFF  /* EQ3_B3_B - [15:0] */
4254 #define WM5100_EQ3_B3_B_SHIFT                        0  /* EQ3_B3_B - [15:0] */
4255 #define WM5100_EQ3_B3_B_WIDTH                       16  /* EQ3_B3_B - [15:0] */
4258  * R3655 (0xE47) - EQ3_12
4260 #define WM5100_EQ3_B3_C_MASK                    0xFFFF  /* EQ3_B3_C - [15:0] */
4261 #define WM5100_EQ3_B3_C_SHIFT                        0  /* EQ3_B3_C - [15:0] */
4262 #define WM5100_EQ3_B3_C_WIDTH                       16  /* EQ3_B3_C - [15:0] */
4265  * R3656 (0xE48) - EQ3_13
4267 #define WM5100_EQ3_B3_PG_MASK                   0xFFFF  /* EQ3_B3_PG - [15:0] */
4268 #define WM5100_EQ3_B3_PG_SHIFT                       0  /* EQ3_B3_PG - [15:0] */
4269 #define WM5100_EQ3_B3_PG_WIDTH                      16  /* EQ3_B3_PG - [15:0] */
4272  * R3657 (0xE49) - EQ3_14
4274 #define WM5100_EQ3_B4_A_MASK                    0xFFFF  /* EQ3_B4_A - [15:0] */
4275 #define WM5100_EQ3_B4_A_SHIFT                        0  /* EQ3_B4_A - [15:0] */
4276 #define WM5100_EQ3_B4_A_WIDTH                       16  /* EQ3_B4_A - [15:0] */
4279  * R3658 (0xE4A) - EQ3_15
4281 #define WM5100_EQ3_B4_B_MASK                    0xFFFF  /* EQ3_B4_B - [15:0] */
4282 #define WM5100_EQ3_B4_B_SHIFT                        0  /* EQ3_B4_B - [15:0] */
4283 #define WM5100_EQ3_B4_B_WIDTH                       16  /* EQ3_B4_B - [15:0] */
4286  * R3659 (0xE4B) - EQ3_16
4288 #define WM5100_EQ3_B4_C_MASK                    0xFFFF  /* EQ3_B4_C - [15:0] */
4289 #define WM5100_EQ3_B4_C_SHIFT                        0  /* EQ3_B4_C - [15:0] */
4290 #define WM5100_EQ3_B4_C_WIDTH                       16  /* EQ3_B4_C - [15:0] */
4293  * R3660 (0xE4C) - EQ3_17
4295 #define WM5100_EQ3_B4_PG_MASK                   0xFFFF  /* EQ3_B4_PG - [15:0] */
4296 #define WM5100_EQ3_B4_PG_SHIFT                       0  /* EQ3_B4_PG - [15:0] */
4297 #define WM5100_EQ3_B4_PG_WIDTH                      16  /* EQ3_B4_PG - [15:0] */
4300  * R3661 (0xE4D) - EQ3_18
4302 #define WM5100_EQ3_B5_A_MASK                    0xFFFF  /* EQ3_B5_A - [15:0] */
4303 #define WM5100_EQ3_B5_A_SHIFT                        0  /* EQ3_B5_A - [15:0] */
4304 #define WM5100_EQ3_B5_A_WIDTH                       16  /* EQ3_B5_A - [15:0] */
4307  * R3662 (0xE4E) - EQ3_19
4309 #define WM5100_EQ3_B5_B_MASK                    0xFFFF  /* EQ3_B5_B - [15:0] */
4310 #define WM5100_EQ3_B5_B_SHIFT                        0  /* EQ3_B5_B - [15:0] */
4311 #define WM5100_EQ3_B5_B_WIDTH                       16  /* EQ3_B5_B - [15:0] */
4314  * R3663 (0xE4F) - EQ3_20
4316 #define WM5100_EQ3_B5_PG_MASK                   0xFFFF  /* EQ3_B5_PG - [15:0] */
4317 #define WM5100_EQ3_B5_PG_SHIFT                       0  /* EQ3_B5_PG - [15:0] */
4318 #define WM5100_EQ3_B5_PG_WIDTH                      16  /* EQ3_B5_PG - [15:0] */
4321  * R3666 (0xE52) - EQ4_1
4323 #define WM5100_EQ4_B1_GAIN_MASK                 0xF800  /* EQ4_B1_GAIN - [15:11] */
4324 #define WM5100_EQ4_B1_GAIN_SHIFT                    11  /* EQ4_B1_GAIN - [15:11] */
4325 #define WM5100_EQ4_B1_GAIN_WIDTH                     5  /* EQ4_B1_GAIN - [15:11] */
4326 #define WM5100_EQ4_B2_GAIN_MASK                 0x07C0  /* EQ4_B2_GAIN - [10:6] */
4327 #define WM5100_EQ4_B2_GAIN_SHIFT                     6  /* EQ4_B2_GAIN - [10:6] */
4328 #define WM5100_EQ4_B2_GAIN_WIDTH                     5  /* EQ4_B2_GAIN - [10:6] */
4329 #define WM5100_EQ4_B3_GAIN_MASK                 0x003E  /* EQ4_B3_GAIN - [5:1] */
4330 #define WM5100_EQ4_B3_GAIN_SHIFT                     1  /* EQ4_B3_GAIN - [5:1] */
4331 #define WM5100_EQ4_B3_GAIN_WIDTH                     5  /* EQ4_B3_GAIN - [5:1] */
4335 #define WM5100_EQ4_ENA_WIDTH                         1  /* EQ4_ENA */
4338  * R3667 (0xE53) - EQ4_2
4340 #define WM5100_EQ4_B4_GAIN_MASK                 0xF800  /* EQ4_B4_GAIN - [15:11] */
4341 #define WM5100_EQ4_B4_GAIN_SHIFT                    11  /* EQ4_B4_GAIN - [15:11] */
4342 #define WM5100_EQ4_B4_GAIN_WIDTH                     5  /* EQ4_B4_GAIN - [15:11] */
4343 #define WM5100_EQ4_B5_GAIN_MASK                 0x07C0  /* EQ4_B5_GAIN - [10:6] */
4344 #define WM5100_EQ4_B5_GAIN_SHIFT                     6  /* EQ4_B5_GAIN - [10:6] */
4345 #define WM5100_EQ4_B5_GAIN_WIDTH                     5  /* EQ4_B5_GAIN - [10:6] */
4348  * R3668 (0xE54) - EQ4_3
4350 #define WM5100_EQ4_B1_A_MASK                    0xFFFF  /* EQ4_B1_A - [15:0] */
4351 #define WM5100_EQ4_B1_A_SHIFT                        0  /* EQ4_B1_A - [15:0] */
4352 #define WM5100_EQ4_B1_A_WIDTH                       16  /* EQ4_B1_A - [15:0] */
4355  * R3669 (0xE55) - EQ4_4
4357 #define WM5100_EQ4_B1_B_MASK                    0xFFFF  /* EQ4_B1_B - [15:0] */
4358 #define WM5100_EQ4_B1_B_SHIFT                        0  /* EQ4_B1_B - [15:0] */
4359 #define WM5100_EQ4_B1_B_WIDTH                       16  /* EQ4_B1_B - [15:0] */
4362  * R3670 (0xE56) - EQ4_5
4364 #define WM5100_EQ4_B1_PG_MASK                   0xFFFF  /* EQ4_B1_PG - [15:0] */
4365 #define WM5100_EQ4_B1_PG_SHIFT                       0  /* EQ4_B1_PG - [15:0] */
4366 #define WM5100_EQ4_B1_PG_WIDTH                      16  /* EQ4_B1_PG - [15:0] */
4369  * R3671 (0xE57) - EQ4_6
4371 #define WM5100_EQ4_B2_A_MASK                    0xFFFF  /* EQ4_B2_A - [15:0] */
4372 #define WM5100_EQ4_B2_A_SHIFT                        0  /* EQ4_B2_A - [15:0] */
4373 #define WM5100_EQ4_B2_A_WIDTH                       16  /* EQ4_B2_A - [15:0] */
4376  * R3672 (0xE58) - EQ4_7
4378 #define WM5100_EQ4_B2_B_MASK                    0xFFFF  /* EQ4_B2_B - [15:0] */
4379 #define WM5100_EQ4_B2_B_SHIFT                        0  /* EQ4_B2_B - [15:0] */
4380 #define WM5100_EQ4_B2_B_WIDTH                       16  /* EQ4_B2_B - [15:0] */
4383  * R3673 (0xE59) - EQ4_8
4385 #define WM5100_EQ4_B2_C_MASK                    0xFFFF  /* EQ4_B2_C - [15:0] */
4386 #define WM5100_EQ4_B2_C_SHIFT                        0  /* EQ4_B2_C - [15:0] */
4387 #define WM5100_EQ4_B2_C_WIDTH                       16  /* EQ4_B2_C - [15:0] */
4390  * R3674 (0xE5A) - EQ4_9
4392 #define WM5100_EQ4_B2_PG_MASK                   0xFFFF  /* EQ4_B2_PG - [15:0] */
4393 #define WM5100_EQ4_B2_PG_SHIFT                       0  /* EQ4_B2_PG - [15:0] */
4394 #define WM5100_EQ4_B2_PG_WIDTH                      16  /* EQ4_B2_PG - [15:0] */
4397  * R3675 (0xE5B) - EQ4_10
4399 #define WM5100_EQ4_B3_A_MASK                    0xFFFF  /* EQ4_B3_A - [15:0] */
4400 #define WM5100_EQ4_B3_A_SHIFT                        0  /* EQ4_B3_A - [15:0] */
4401 #define WM5100_EQ4_B3_A_WIDTH                       16  /* EQ4_B3_A - [15:0] */
4404  * R3676 (0xE5C) - EQ4_11
4406 #define WM5100_EQ4_B3_B_MASK                    0xFFFF  /* EQ4_B3_B - [15:0] */
4407 #define WM5100_EQ4_B3_B_SHIFT                        0  /* EQ4_B3_B - [15:0] */
4408 #define WM5100_EQ4_B3_B_WIDTH                       16  /* EQ4_B3_B - [15:0] */
4411  * R3677 (0xE5D) - EQ4_12
4413 #define WM5100_EQ4_B3_C_MASK                    0xFFFF  /* EQ4_B3_C - [15:0] */
4414 #define WM5100_EQ4_B3_C_SHIFT                        0  /* EQ4_B3_C - [15:0] */
4415 #define WM5100_EQ4_B3_C_WIDTH                       16  /* EQ4_B3_C - [15:0] */
4418  * R3678 (0xE5E) - EQ4_13
4420 #define WM5100_EQ4_B3_PG_MASK                   0xFFFF  /* EQ4_B3_PG - [15:0] */
4421 #define WM5100_EQ4_B3_PG_SHIFT                       0  /* EQ4_B3_PG - [15:0] */
4422 #define WM5100_EQ4_B3_PG_WIDTH                      16  /* EQ4_B3_PG - [15:0] */
4425  * R3679 (0xE5F) - EQ4_14
4427 #define WM5100_EQ4_B4_A_MASK                    0xFFFF  /* EQ4_B4_A - [15:0] */
4428 #define WM5100_EQ4_B4_A_SHIFT                        0  /* EQ4_B4_A - [15:0] */
4429 #define WM5100_EQ4_B4_A_WIDTH                       16  /* EQ4_B4_A - [15:0] */
4432  * R3680 (0xE60) - EQ4_15
4434 #define WM5100_EQ4_B4_B_MASK                    0xFFFF  /* EQ4_B4_B - [15:0] */
4435 #define WM5100_EQ4_B4_B_SHIFT                        0  /* EQ4_B4_B - [15:0] */
4436 #define WM5100_EQ4_B4_B_WIDTH                       16  /* EQ4_B4_B - [15:0] */
4439  * R3681 (0xE61) - EQ4_16
4441 #define WM5100_EQ4_B4_C_MASK                    0xFFFF  /* EQ4_B4_C - [15:0] */
4442 #define WM5100_EQ4_B4_C_SHIFT                        0  /* EQ4_B4_C - [15:0] */
4443 #define WM5100_EQ4_B4_C_WIDTH                       16  /* EQ4_B4_C - [15:0] */
4446  * R3682 (0xE62) - EQ4_17
4448 #define WM5100_EQ4_B4_PG_MASK                   0xFFFF  /* EQ4_B4_PG - [15:0] */
4449 #define WM5100_EQ4_B4_PG_SHIFT                       0  /* EQ4_B4_PG - [15:0] */
4450 #define WM5100_EQ4_B4_PG_WIDTH                      16  /* EQ4_B4_PG - [15:0] */
4453  * R3683 (0xE63) - EQ4_18
4455 #define WM5100_EQ4_B5_A_MASK                    0xFFFF  /* EQ4_B5_A - [15:0] */
4456 #define WM5100_EQ4_B5_A_SHIFT                        0  /* EQ4_B5_A - [15:0] */
4457 #define WM5100_EQ4_B5_A_WIDTH                       16  /* EQ4_B5_A - [15:0] */
4460  * R3684 (0xE64) - EQ4_19
4462 #define WM5100_EQ4_B5_B_MASK                    0xFFFF  /* EQ4_B5_B - [15:0] */
4463 #define WM5100_EQ4_B5_B_SHIFT                        0  /* EQ4_B5_B - [15:0] */
4464 #define WM5100_EQ4_B5_B_WIDTH                       16  /* EQ4_B5_B - [15:0] */
4467  * R3685 (0xE65) - EQ4_20
4469 #define WM5100_EQ4_B5_PG_MASK                   0xFFFF  /* EQ4_B5_PG - [15:0] */
4470 #define WM5100_EQ4_B5_PG_SHIFT                       0  /* EQ4_B5_PG - [15:0] */
4471 #define WM5100_EQ4_B5_PG_WIDTH                      16  /* EQ4_B5_PG - [15:0] */
4474  * R3712 (0xE80) - DRC1 ctrl1
4476 #define WM5100_DRC_SIG_DET_RMS_MASK             0xF800  /* DRC_SIG_DET_RMS - [15:11] */
4477 #define WM5100_DRC_SIG_DET_RMS_SHIFT                11  /* DRC_SIG_DET_RMS - [15:11] */
4478 #define WM5100_DRC_SIG_DET_RMS_WIDTH                 5  /* DRC_SIG_DET_RMS - [15:11] */
4479 #define WM5100_DRC_SIG_DET_PK_MASK              0x0600  /* DRC_SIG_DET_PK - [10:9] */
4480 #define WM5100_DRC_SIG_DET_PK_SHIFT                  9  /* DRC_SIG_DET_PK - [10:9] */
4481 #define WM5100_DRC_SIG_DET_PK_WIDTH                  2  /* DRC_SIG_DET_PK - [10:9] */
4485 #define WM5100_DRC_NG_ENA_WIDTH                      1  /* DRC_NG_ENA */
4489 #define WM5100_DRC_SIG_DET_MODE_WIDTH                1  /* DRC_SIG_DET_MODE */
4493 #define WM5100_DRC_SIG_DET_WIDTH                     1  /* DRC_SIG_DET */
4497 #define WM5100_DRC_KNEE2_OP_ENA_WIDTH                1  /* DRC_KNEE2_OP_ENA */
4501 #define WM5100_DRC_QR_WIDTH                          1  /* DRC_QR */
4505 #define WM5100_DRC_ANTICLIP_WIDTH                    1  /* DRC_ANTICLIP */
4508 #define WM5100_DRCL_ENA_SHIFT                        1  /* DRCL_ENA */
4509 #define WM5100_DRCL_ENA_WIDTH                        1  /* DRCL_ENA */
4513 #define WM5100_DRCR_ENA_WIDTH                        1  /* DRCR_ENA */
4516  * R3713 (0xE81) - DRC1 ctrl2
4518 #define WM5100_DRC_ATK_MASK                     0x1E00  /* DRC_ATK - [12:9] */
4519 #define WM5100_DRC_ATK_SHIFT                         9  /* DRC_ATK - [12:9] */
4520 #define WM5100_DRC_ATK_WIDTH                         4  /* DRC_ATK - [12:9] */
4521 #define WM5100_DRC_DCY_MASK                     0x01E0  /* DRC_DCY - [8:5] */
4522 #define WM5100_DRC_DCY_SHIFT                         5  /* DRC_DCY - [8:5] */
4523 #define WM5100_DRC_DCY_WIDTH                         4  /* DRC_DCY - [8:5] */
4524 #define WM5100_DRC_MINGAIN_MASK                 0x001C  /* DRC_MINGAIN - [4:2] */
4525 #define WM5100_DRC_MINGAIN_SHIFT                     2  /* DRC_MINGAIN - [4:2] */
4526 #define WM5100_DRC_MINGAIN_WIDTH                     3  /* DRC_MINGAIN - [4:2] */
4527 #define WM5100_DRC_MAXGAIN_MASK                 0x0003  /* DRC_MAXGAIN - [1:0] */
4528 #define WM5100_DRC_MAXGAIN_SHIFT                     0  /* DRC_MAXGAIN - [1:0] */
4529 #define WM5100_DRC_MAXGAIN_WIDTH                     2  /* DRC_MAXGAIN - [1:0] */
4532  * R3714 (0xE82) - DRC1 ctrl3
4534 #define WM5100_DRC_NG_MINGAIN_MASK              0xF000  /* DRC_NG_MINGAIN - [15:12] */
4535 #define WM5100_DRC_NG_MINGAIN_SHIFT                 12  /* DRC_NG_MINGAIN - [15:12] */
4536 #define WM5100_DRC_NG_MINGAIN_WIDTH                  4  /* DRC_NG_MINGAIN - [15:12] */
4537 #define WM5100_DRC_NG_EXP_MASK                  0x0C00  /* DRC_NG_EXP - [11:10] */
4538 #define WM5100_DRC_NG_EXP_SHIFT                     10  /* DRC_NG_EXP - [11:10] */
4539 #define WM5100_DRC_NG_EXP_WIDTH                      2  /* DRC_NG_EXP - [11:10] */
4540 #define WM5100_DRC_QR_THR_MASK                  0x0300  /* DRC_QR_THR - [9:8] */
4541 #define WM5100_DRC_QR_THR_SHIFT                      8  /* DRC_QR_THR - [9:8] */
4542 #define WM5100_DRC_QR_THR_WIDTH                      2  /* DRC_QR_THR - [9:8] */
4543 #define WM5100_DRC_QR_DCY_MASK                  0x00C0  /* DRC_QR_DCY - [7:6] */
4544 #define WM5100_DRC_QR_DCY_SHIFT                      6  /* DRC_QR_DCY - [7:6] */
4545 #define WM5100_DRC_QR_DCY_WIDTH                      2  /* DRC_QR_DCY - [7:6] */
4546 #define WM5100_DRC_HI_COMP_MASK                 0x0038  /* DRC_HI_COMP - [5:3] */
4547 #define WM5100_DRC_HI_COMP_SHIFT                     3  /* DRC_HI_COMP - [5:3] */
4548 #define WM5100_DRC_HI_COMP_WIDTH                     3  /* DRC_HI_COMP - [5:3] */
4549 #define WM5100_DRC_LO_COMP_MASK                 0x0007  /* DRC_LO_COMP - [2:0] */
4550 #define WM5100_DRC_LO_COMP_SHIFT                     0  /* DRC_LO_COMP - [2:0] */
4551 #define WM5100_DRC_LO_COMP_WIDTH                     3  /* DRC_LO_COMP - [2:0] */
4554  * R3715 (0xE83) - DRC1 ctrl4
4556 #define WM5100_DRC_KNEE_IP_MASK                 0x07E0  /* DRC_KNEE_IP - [10:5] */
4557 #define WM5100_DRC_KNEE_IP_SHIFT                     5  /* DRC_KNEE_IP - [10:5] */
4558 #define WM5100_DRC_KNEE_IP_WIDTH                     6  /* DRC_KNEE_IP - [10:5] */
4559 #define WM5100_DRC_KNEE_OP_MASK                 0x001F  /* DRC_KNEE_OP - [4:0] */
4560 #define WM5100_DRC_KNEE_OP_SHIFT                     0  /* DRC_KNEE_OP - [4:0] */
4561 #define WM5100_DRC_KNEE_OP_WIDTH                     5  /* DRC_KNEE_OP - [4:0] */
4564  * R3716 (0xE84) - DRC1 ctrl5
4566 #define WM5100_DRC_KNEE2_IP_MASK                0x03E0  /* DRC_KNEE2_IP - [9:5] */
4567 #define WM5100_DRC_KNEE2_IP_SHIFT                    5  /* DRC_KNEE2_IP - [9:5] */
4568 #define WM5100_DRC_KNEE2_IP_WIDTH                    5  /* DRC_KNEE2_IP - [9:5] */
4569 #define WM5100_DRC_KNEE2_OP_MASK                0x001F  /* DRC_KNEE2_OP - [4:0] */
4570 #define WM5100_DRC_KNEE2_OP_SHIFT                    0  /* DRC_KNEE2_OP - [4:0] */
4571 #define WM5100_DRC_KNEE2_OP_WIDTH                    5  /* DRC_KNEE2_OP - [4:0] */
4574  * R3776 (0xEC0) - HPLPF1_1
4578 #define WM5100_LHPF1_MODE_SHIFT                      1  /* LHPF1_MODE */
4579 #define WM5100_LHPF1_MODE_WIDTH                      1  /* LHPF1_MODE */
4583 #define WM5100_LHPF1_ENA_WIDTH                       1  /* LHPF1_ENA */
4586  * R3777 (0xEC1) - HPLPF1_2
4588 #define WM5100_LHPF1_COEFF_MASK                 0xFFFF  /* LHPF1_COEFF - [15:0] */
4589 #define WM5100_LHPF1_COEFF_SHIFT                     0  /* LHPF1_COEFF - [15:0] */
4590 #define WM5100_LHPF1_COEFF_WIDTH                    16  /* LHPF1_COEFF - [15:0] */
4593  * R3780 (0xEC4) - HPLPF2_1
4597 #define WM5100_LHPF2_MODE_SHIFT                      1  /* LHPF2_MODE */
4598 #define WM5100_LHPF2_MODE_WIDTH                      1  /* LHPF2_MODE */
4602 #define WM5100_LHPF2_ENA_WIDTH                       1  /* LHPF2_ENA */
4605  * R3781 (0xEC5) - HPLPF2_2
4607 #define WM5100_LHPF2_COEFF_MASK                 0xFFFF  /* LHPF2_COEFF - [15:0] */
4608 #define WM5100_LHPF2_COEFF_SHIFT                     0  /* LHPF2_COEFF - [15:0] */
4609 #define WM5100_LHPF2_COEFF_WIDTH                    16  /* LHPF2_COEFF - [15:0] */
4612  * R3784 (0xEC8) - HPLPF3_1
4616 #define WM5100_LHPF3_MODE_SHIFT                      1  /* LHPF3_MODE */
4617 #define WM5100_LHPF3_MODE_WIDTH                      1  /* LHPF3_MODE */
4621 #define WM5100_LHPF3_ENA_WIDTH                       1  /* LHPF3_ENA */
4624  * R3785 (0xEC9) - HPLPF3_2
4626 #define WM5100_LHPF3_COEFF_MASK                 0xFFFF  /* LHPF3_COEFF - [15:0] */
4627 #define WM5100_LHPF3_COEFF_SHIFT                     0  /* LHPF3_COEFF - [15:0] */
4628 #define WM5100_LHPF3_COEFF_WIDTH                    16  /* LHPF3_COEFF - [15:0] */
4631  * R3788 (0xECC) - HPLPF4_1
4635 #define WM5100_LHPF4_MODE_SHIFT                      1  /* LHPF4_MODE */
4636 #define WM5100_LHPF4_MODE_WIDTH                      1  /* LHPF4_MODE */
4640 #define WM5100_LHPF4_ENA_WIDTH                       1  /* LHPF4_ENA */
4643  * R3789 (0xECD) - HPLPF4_2
4645 #define WM5100_LHPF4_COEFF_MASK                 0xFFFF  /* LHPF4_COEFF - [15:0] */
4646 #define WM5100_LHPF4_COEFF_SHIFT                     0  /* LHPF4_COEFF - [15:0] */
4647 #define WM5100_LHPF4_COEFF_WIDTH                    16  /* LHPF4_COEFF - [15:0] */
4650  * R4132 (0x1024) - DSP2 Control 30
4652 #define WM5100_DSP2_RATE_MASK                   0xC000  /* DSP2_RATE - [15:14] */
4653 #define WM5100_DSP2_RATE_SHIFT                      14  /* DSP2_RATE - [15:14] */
4654 #define WM5100_DSP2_RATE_WIDTH                       2  /* DSP2_RATE - [15:14] */
4658 #define WM5100_DSP2_DBG_CLK_ENA_WIDTH                1  /* DSP2_DBG_CLK_ENA */
4662 #define WM5100_DSP2_SYS_ENA_WIDTH                    1  /* DSP2_SYS_ENA */
4665 #define WM5100_DSP2_CORE_ENA_SHIFT                   1  /* DSP2_CORE_ENA */
4666 #define WM5100_DSP2_CORE_ENA_WIDTH                   1  /* DSP2_CORE_ENA */
4670 #define WM5100_DSP2_START_WIDTH                      1  /* DSP2_START */
4673  * R3876 (0xF24) - DSP1 Control 30
4675 #define WM5100_DSP1_RATE_MASK                   0xC000  /* DSP1_RATE - [15:14] */
4676 #define WM5100_DSP1_RATE_SHIFT                      14  /* DSP1_RATE - [15:14] */
4677 #define WM5100_DSP1_RATE_WIDTH                       2  /* DSP1_RATE - [15:14] */
4681 #define WM5100_DSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */
4685 #define WM5100_DSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
4688 #define WM5100_DSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
4689 #define WM5100_DSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
4693 #define WM5100_DSP1_START_WIDTH                      1  /* DSP1_START */
4696  * R4388 (0x1124) - DSP3 Control 30
4698 #define WM5100_DSP3_RATE_MASK                   0xC000  /* DSP3_RATE - [15:14] */
4699 #define WM5100_DSP3_RATE_SHIFT                      14  /* DSP3_RATE - [15:14] */
4700 #define WM5100_DSP3_RATE_WIDTH                       2  /* DSP3_RATE - [15:14] */
4704 #define WM5100_DSP3_DBG_CLK_ENA_WIDTH                1  /* DSP3_DBG_CLK_ENA */
4708 #define WM5100_DSP3_SYS_ENA_WIDTH                    1  /* DSP3_SYS_ENA */
4711 #define WM5100_DSP3_CORE_ENA_SHIFT                   1  /* DSP3_CORE_ENA */
4712 #define WM5100_DSP3_CORE_ENA_WIDTH                   1  /* DSP3_CORE_ENA */
4716 #define WM5100_DSP3_START_WIDTH                      1  /* DSP3_START */
4719  * R16384 (0x4000) - DSP1 DM 0
4721 #define WM5100_DSP1_DM_START_1_MASK             0x00FF  /* DSP1_DM_START - [7:0] */
4722 #define WM5100_DSP1_DM_START_1_SHIFT                 0  /* DSP1_DM_START - [7:0] */
4723 #define WM5100_DSP1_DM_START_1_WIDTH                 8  /* DSP1_DM_START - [7:0] */
4726  * R16385 (0x4001) - DSP1 DM 1
4728 #define WM5100_DSP1_DM_START_MASK               0xFFFF  /* DSP1_DM_START - [15:0] */
4729 #define WM5100_DSP1_DM_START_SHIFT                   0  /* DSP1_DM_START - [15:0] */
4730 #define WM5100_DSP1_DM_START_WIDTH                  16  /* DSP1_DM_START - [15:0] */
4733  * R16386 (0x4002) - DSP1 DM 2
4735 #define WM5100_DSP1_DM_1_1_MASK                 0x00FF  /* DSP1_DM_1 - [7:0] */
4736 #define WM5100_DSP1_DM_1_1_SHIFT                     0  /* DSP1_DM_1 - [7:0] */
4737 #define WM5100_DSP1_DM_1_1_WIDTH                     8  /* DSP1_DM_1 - [7:0] */
4740  * R16387 (0x4003) - DSP1 DM 3
4742 #define WM5100_DSP1_DM_1_MASK                   0xFFFF  /* DSP1_DM_1 - [15:0] */
4743 #define WM5100_DSP1_DM_1_SHIFT                       0  /* DSP1_DM_1 - [15:0] */
4744 #define WM5100_DSP1_DM_1_WIDTH                      16  /* DSP1_DM_1 - [15:0] */
4747  * R16892 (0x41FC) - DSP1 DM 508
4749 #define WM5100_DSP1_DM_254_1_MASK               0x00FF  /* DSP1_DM_254 - [7:0] */
4750 #define WM5100_DSP1_DM_254_1_SHIFT                   0  /* DSP1_DM_254 - [7:0] */
4751 #define WM5100_DSP1_DM_254_1_WIDTH                   8  /* DSP1_DM_254 - [7:0] */
4754  * R16893 (0x41FD) - DSP1 DM 509
4756 #define WM5100_DSP1_DM_254_MASK                 0xFFFF  /* DSP1_DM_254 - [15:0] */
4757 #define WM5100_DSP1_DM_254_SHIFT                     0  /* DSP1_DM_254 - [15:0] */
4758 #define WM5100_DSP1_DM_254_WIDTH                    16  /* DSP1_DM_254 - [15:0] */
4761  * R16894 (0x41FE) - DSP1 DM 510
4763 #define WM5100_DSP1_DM_END_1_MASK               0x00FF  /* DSP1_DM_END - [7:0] */
4764 #define WM5100_DSP1_DM_END_1_SHIFT                   0  /* DSP1_DM_END - [7:0] */
4765 #define WM5100_DSP1_DM_END_1_WIDTH                   8  /* DSP1_DM_END - [7:0] */
4768  * R16895 (0x41FF) - DSP1 DM 511
4770 #define WM5100_DSP1_DM_END_MASK                 0xFFFF  /* DSP1_DM_END - [15:0] */
4771 #define WM5100_DSP1_DM_END_SHIFT                     0  /* DSP1_DM_END - [15:0] */
4772 #define WM5100_DSP1_DM_END_WIDTH                    16  /* DSP1_DM_END - [15:0] */
4775  * R18432 (0x4800) - DSP1 PM 0
4777 #define WM5100_DSP1_PM_START_2_MASK             0x00FF  /* DSP1_PM_START - [7:0] */
4778 #define WM5100_DSP1_PM_START_2_SHIFT                 0  /* DSP1_PM_START - [7:0] */
4779 #define WM5100_DSP1_PM_START_2_WIDTH                 8  /* DSP1_PM_START - [7:0] */
4782  * R18433 (0x4801) - DSP1 PM 1
4784 #define WM5100_DSP1_PM_START_1_MASK             0xFFFF  /* DSP1_PM_START - [15:0] */
4785 #define WM5100_DSP1_PM_START_1_SHIFT                 0  /* DSP1_PM_START - [15:0] */
4786 #define WM5100_DSP1_PM_START_1_WIDTH                16  /* DSP1_PM_START - [15:0] */
4789  * R18434 (0x4802) - DSP1 PM 2
4791 #define WM5100_DSP1_PM_START_MASK               0xFFFF  /* DSP1_PM_START - [15:0] */
4792 #define WM5100_DSP1_PM_START_SHIFT                   0  /* DSP1_PM_START - [15:0] */
4793 #define WM5100_DSP1_PM_START_WIDTH                  16  /* DSP1_PM_START - [15:0] */
4796  * R18435 (0x4803) - DSP1 PM 3
4798 #define WM5100_DSP1_PM_1_2_MASK                 0x00FF  /* DSP1_PM_1 - [7:0] */
4799 #define WM5100_DSP1_PM_1_2_SHIFT                     0  /* DSP1_PM_1 - [7:0] */
4800 #define WM5100_DSP1_PM_1_2_WIDTH                     8  /* DSP1_PM_1 - [7:0] */
4803  * R18436 (0x4804) - DSP1 PM 4
4805 #define WM5100_DSP1_PM_1_1_MASK                 0xFFFF  /* DSP1_PM_1 - [15:0] */
4806 #define WM5100_DSP1_PM_1_1_SHIFT                     0  /* DSP1_PM_1 - [15:0] */
4807 #define WM5100_DSP1_PM_1_1_WIDTH                    16  /* DSP1_PM_1 - [15:0] */
4810  * R18437 (0x4805) - DSP1 PM 5
4812 #define WM5100_DSP1_PM_1_MASK                   0xFFFF  /* DSP1_PM_1 - [15:0] */
4813 #define WM5100_DSP1_PM_1_SHIFT                       0  /* DSP1_PM_1 - [15:0] */
4814 #define WM5100_DSP1_PM_1_WIDTH                      16  /* DSP1_PM_1 - [15:0] */
4817  * R19962 (0x4DFA) - DSP1 PM 1530
4819 #define WM5100_DSP1_PM_510_2_MASK               0x00FF  /* DSP1_PM_510 - [7:0] */
4820 #define WM5100_DSP1_PM_510_2_SHIFT                   0  /* DSP1_PM_510 - [7:0] */
4821 #define WM5100_DSP1_PM_510_2_WIDTH                   8  /* DSP1_PM_510 - [7:0] */
4824  * R19963 (0x4DFB) - DSP1 PM 1531
4826 #define WM5100_DSP1_PM_510_1_MASK               0xFFFF  /* DSP1_PM_510 - [15:0] */
4827 #define WM5100_DSP1_PM_510_1_SHIFT                   0  /* DSP1_PM_510 - [15:0] */
4828 #define WM5100_DSP1_PM_510_1_WIDTH                  16  /* DSP1_PM_510 - [15:0] */
4831  * R19964 (0x4DFC) - DSP1 PM 1532
4833 #define WM5100_DSP1_PM_510_MASK                 0xFFFF  /* DSP1_PM_510 - [15:0] */
4834 #define WM5100_DSP1_PM_510_SHIFT                     0  /* DSP1_PM_510 - [15:0] */
4835 #define WM5100_DSP1_PM_510_WIDTH                    16  /* DSP1_PM_510 - [15:0] */
4838  * R19965 (0x4DFD) - DSP1 PM 1533
4840 #define WM5100_DSP1_PM_END_2_MASK               0x00FF  /* DSP1_PM_END - [7:0] */
4841 #define WM5100_DSP1_PM_END_2_SHIFT                   0  /* DSP1_PM_END - [7:0] */
4842 #define WM5100_DSP1_PM_END_2_WIDTH                   8  /* DSP1_PM_END - [7:0] */
4845  * R19966 (0x4DFE) - DSP1 PM 1534
4847 #define WM5100_DSP1_PM_END_1_MASK               0xFFFF  /* DSP1_PM_END - [15:0] */
4848 #define WM5100_DSP1_PM_END_1_SHIFT                   0  /* DSP1_PM_END - [15:0] */
4849 #define WM5100_DSP1_PM_END_1_WIDTH                  16  /* DSP1_PM_END - [15:0] */
4852  * R19967 (0x4DFF) - DSP1 PM 1535
4854 #define WM5100_DSP1_PM_END_MASK                 0xFFFF  /* DSP1_PM_END - [15:0] */
4855 #define WM5100_DSP1_PM_END_SHIFT                     0  /* DSP1_PM_END - [15:0] */
4856 #define WM5100_DSP1_PM_END_WIDTH                    16  /* DSP1_PM_END - [15:0] */
4859  * R20480 (0x5000) - DSP1 ZM 0
4861 #define WM5100_DSP1_ZM_START_1_MASK             0x00FF  /* DSP1_ZM_START - [7:0] */
4862 #define WM5100_DSP1_ZM_START_1_SHIFT                 0  /* DSP1_ZM_START - [7:0] */
4863 #define WM5100_DSP1_ZM_START_1_WIDTH                 8  /* DSP1_ZM_START - [7:0] */
4866  * R20481 (0x5001) - DSP1 ZM 1
4868 #define WM5100_DSP1_ZM_START_MASK               0xFFFF  /* DSP1_ZM_START - [15:0] */
4869 #define WM5100_DSP1_ZM_START_SHIFT                   0  /* DSP1_ZM_START - [15:0] */
4870 #define WM5100_DSP1_ZM_START_WIDTH                  16  /* DSP1_ZM_START - [15:0] */
4873  * R20482 (0x5002) - DSP1 ZM 2
4875 #define WM5100_DSP1_ZM_1_1_MASK                 0x00FF  /* DSP1_ZM_1 - [7:0] */
4876 #define WM5100_DSP1_ZM_1_1_SHIFT                     0  /* DSP1_ZM_1 - [7:0] */
4877 #define WM5100_DSP1_ZM_1_1_WIDTH                     8  /* DSP1_ZM_1 - [7:0] */
4880  * R20483 (0x5003) - DSP1 ZM 3
4882 #define WM5100_DSP1_ZM_1_MASK                   0xFFFF  /* DSP1_ZM_1 - [15:0] */
4883 #define WM5100_DSP1_ZM_1_SHIFT                       0  /* DSP1_ZM_1 - [15:0] */
4884 #define WM5100_DSP1_ZM_1_WIDTH                      16  /* DSP1_ZM_1 - [15:0] */
4887  * R22524 (0x57FC) - DSP1 ZM 2044
4889 #define WM5100_DSP1_ZM_1022_1_MASK              0x00FF  /* DSP1_ZM_1022 - [7:0] */
4890 #define WM5100_DSP1_ZM_1022_1_SHIFT                  0  /* DSP1_ZM_1022 - [7:0] */
4891 #define WM5100_DSP1_ZM_1022_1_WIDTH                  8  /* DSP1_ZM_1022 - [7:0] */
4894  * R22525 (0x57FD) - DSP1 ZM 2045
4896 #define WM5100_DSP1_ZM_1022_MASK                0xFFFF  /* DSP1_ZM_1022 - [15:0] */
4897 #define WM5100_DSP1_ZM_1022_SHIFT                    0  /* DSP1_ZM_1022 - [15:0] */
4898 #define WM5100_DSP1_ZM_1022_WIDTH                   16  /* DSP1_ZM_1022 - [15:0] */
4901  * R22526 (0x57FE) - DSP1 ZM 2046
4903 #define WM5100_DSP1_ZM_END_1_MASK               0x00FF  /* DSP1_ZM_END - [7:0] */
4904 #define WM5100_DSP1_ZM_END_1_SHIFT                   0  /* DSP1_ZM_END - [7:0] */
4905 #define WM5100_DSP1_ZM_END_1_WIDTH                   8  /* DSP1_ZM_END - [7:0] */
4908  * R22527 (0x57FF) - DSP1 ZM 2047
4910 #define WM5100_DSP1_ZM_END_MASK                 0xFFFF  /* DSP1_ZM_END - [15:0] */
4911 #define WM5100_DSP1_ZM_END_SHIFT                     0  /* DSP1_ZM_END - [15:0] */
4912 #define WM5100_DSP1_ZM_END_WIDTH                    16  /* DSP1_ZM_END - [15:0] */
4915  * R24576 (0x6000) - DSP2 DM 0
4917 #define WM5100_DSP2_DM_START_1_MASK             0x00FF  /* DSP2_DM_START - [7:0] */
4918 #define WM5100_DSP2_DM_START_1_SHIFT                 0  /* DSP2_DM_START - [7:0] */
4919 #define WM5100_DSP2_DM_START_1_WIDTH                 8  /* DSP2_DM_START - [7:0] */
4922  * R24577 (0x6001) - DSP2 DM 1
4924 #define WM5100_DSP2_DM_START_MASK               0xFFFF  /* DSP2_DM_START - [15:0] */
4925 #define WM5100_DSP2_DM_START_SHIFT                   0  /* DSP2_DM_START - [15:0] */
4926 #define WM5100_DSP2_DM_START_WIDTH                  16  /* DSP2_DM_START - [15:0] */
4929  * R24578 (0x6002) - DSP2 DM 2
4931 #define WM5100_DSP2_DM_1_1_MASK                 0x00FF  /* DSP2_DM_1 - [7:0] */
4932 #define WM5100_DSP2_DM_1_1_SHIFT                     0  /* DSP2_DM_1 - [7:0] */
4933 #define WM5100_DSP2_DM_1_1_WIDTH                     8  /* DSP2_DM_1 - [7:0] */
4936  * R24579 (0x6003) - DSP2 DM 3
4938 #define WM5100_DSP2_DM_1_MASK                   0xFFFF  /* DSP2_DM_1 - [15:0] */
4939 #define WM5100_DSP2_DM_1_SHIFT                       0  /* DSP2_DM_1 - [15:0] */
4940 #define WM5100_DSP2_DM_1_WIDTH                      16  /* DSP2_DM_1 - [15:0] */
4943  * R25084 (0x61FC) - DSP2 DM 508
4945 #define WM5100_DSP2_DM_254_1_MASK               0x00FF  /* DSP2_DM_254 - [7:0] */
4946 #define WM5100_DSP2_DM_254_1_SHIFT                   0  /* DSP2_DM_254 - [7:0] */
4947 #define WM5100_DSP2_DM_254_1_WIDTH                   8  /* DSP2_DM_254 - [7:0] */
4950  * R25085 (0x61FD) - DSP2 DM 509
4952 #define WM5100_DSP2_DM_254_MASK                 0xFFFF  /* DSP2_DM_254 - [15:0] */
4953 #define WM5100_DSP2_DM_254_SHIFT                     0  /* DSP2_DM_254 - [15:0] */
4954 #define WM5100_DSP2_DM_254_WIDTH                    16  /* DSP2_DM_254 - [15:0] */
4957  * R25086 (0x61FE) - DSP2 DM 510
4959 #define WM5100_DSP2_DM_END_1_MASK               0x00FF  /* DSP2_DM_END - [7:0] */
4960 #define WM5100_DSP2_DM_END_1_SHIFT                   0  /* DSP2_DM_END - [7:0] */
4961 #define WM5100_DSP2_DM_END_1_WIDTH                   8  /* DSP2_DM_END - [7:0] */
4964  * R25087 (0x61FF) - DSP2 DM 511
4966 #define WM5100_DSP2_DM_END_MASK                 0xFFFF  /* DSP2_DM_END - [15:0] */
4967 #define WM5100_DSP2_DM_END_SHIFT                     0  /* DSP2_DM_END - [15:0] */
4968 #define WM5100_DSP2_DM_END_WIDTH                    16  /* DSP2_DM_END - [15:0] */
4971  * R26624 (0x6800) - DSP2 PM 0
4973 #define WM5100_DSP2_PM_START_2_MASK             0x00FF  /* DSP2_PM_START - [7:0] */
4974 #define WM5100_DSP2_PM_START_2_SHIFT                 0  /* DSP2_PM_START - [7:0] */
4975 #define WM5100_DSP2_PM_START_2_WIDTH                 8  /* DSP2_PM_START - [7:0] */
4978  * R26625 (0x6801) - DSP2 PM 1
4980 #define WM5100_DSP2_PM_START_1_MASK             0xFFFF  /* DSP2_PM_START - [15:0] */
4981 #define WM5100_DSP2_PM_START_1_SHIFT                 0  /* DSP2_PM_START - [15:0] */
4982 #define WM5100_DSP2_PM_START_1_WIDTH                16  /* DSP2_PM_START - [15:0] */
4985  * R26626 (0x6802) - DSP2 PM 2
4987 #define WM5100_DSP2_PM_START_MASK               0xFFFF  /* DSP2_PM_START - [15:0] */
4988 #define WM5100_DSP2_PM_START_SHIFT                   0  /* DSP2_PM_START - [15:0] */
4989 #define WM5100_DSP2_PM_START_WIDTH                  16  /* DSP2_PM_START - [15:0] */
4992  * R26627 (0x6803) - DSP2 PM 3
4994 #define WM5100_DSP2_PM_1_2_MASK                 0x00FF  /* DSP2_PM_1 - [7:0] */
4995 #define WM5100_DSP2_PM_1_2_SHIFT                     0  /* DSP2_PM_1 - [7:0] */
4996 #define WM5100_DSP2_PM_1_2_WIDTH                     8  /* DSP2_PM_1 - [7:0] */
4999  * R26628 (0x6804) - DSP2 PM 4
5001 #define WM5100_DSP2_PM_1_1_MASK                 0xFFFF  /* DSP2_PM_1 - [15:0] */
5002 #define WM5100_DSP2_PM_1_1_SHIFT                     0  /* DSP2_PM_1 - [15:0] */
5003 #define WM5100_DSP2_PM_1_1_WIDTH                    16  /* DSP2_PM_1 - [15:0] */
5006  * R26629 (0x6805) - DSP2 PM 5
5008 #define WM5100_DSP2_PM_1_MASK                   0xFFFF  /* DSP2_PM_1 - [15:0] */
5009 #define WM5100_DSP2_PM_1_SHIFT                       0  /* DSP2_PM_1 - [15:0] */
5010 #define WM5100_DSP2_PM_1_WIDTH                      16  /* DSP2_PM_1 - [15:0] */
5013  * R28154 (0x6DFA) - DSP2 PM 1530
5015 #define WM5100_DSP2_PM_510_2_MASK               0x00FF  /* DSP2_PM_510 - [7:0] */
5016 #define WM5100_DSP2_PM_510_2_SHIFT                   0  /* DSP2_PM_510 - [7:0] */
5017 #define WM5100_DSP2_PM_510_2_WIDTH                   8  /* DSP2_PM_510 - [7:0] */
5020  * R28155 (0x6DFB) - DSP2 PM 1531
5022 #define WM5100_DSP2_PM_510_1_MASK               0xFFFF  /* DSP2_PM_510 - [15:0] */
5023 #define WM5100_DSP2_PM_510_1_SHIFT                   0  /* DSP2_PM_510 - [15:0] */
5024 #define WM5100_DSP2_PM_510_1_WIDTH                  16  /* DSP2_PM_510 - [15:0] */
5027  * R28156 (0x6DFC) - DSP2 PM 1532
5029 #define WM5100_DSP2_PM_510_MASK                 0xFFFF  /* DSP2_PM_510 - [15:0] */
5030 #define WM5100_DSP2_PM_510_SHIFT                     0  /* DSP2_PM_510 - [15:0] */
5031 #define WM5100_DSP2_PM_510_WIDTH                    16  /* DSP2_PM_510 - [15:0] */
5034  * R28157 (0x6DFD) - DSP2 PM 1533
5036 #define WM5100_DSP2_PM_END_2_MASK               0x00FF  /* DSP2_PM_END - [7:0] */
5037 #define WM5100_DSP2_PM_END_2_SHIFT                   0  /* DSP2_PM_END - [7:0] */
5038 #define WM5100_DSP2_PM_END_2_WIDTH                   8  /* DSP2_PM_END - [7:0] */
5041  * R28158 (0x6DFE) - DSP2 PM 1534
5043 #define WM5100_DSP2_PM_END_1_MASK               0xFFFF  /* DSP2_PM_END - [15:0] */
5044 #define WM5100_DSP2_PM_END_1_SHIFT                   0  /* DSP2_PM_END - [15:0] */
5045 #define WM5100_DSP2_PM_END_1_WIDTH                  16  /* DSP2_PM_END - [15:0] */
5048  * R28159 (0x6DFF) - DSP2 PM 1535
5050 #define WM5100_DSP2_PM_END_MASK                 0xFFFF  /* DSP2_PM_END - [15:0] */
5051 #define WM5100_DSP2_PM_END_SHIFT                     0  /* DSP2_PM_END - [15:0] */
5052 #define WM5100_DSP2_PM_END_WIDTH                    16  /* DSP2_PM_END - [15:0] */
5055  * R28672 (0x7000) - DSP2 ZM 0
5057 #define WM5100_DSP2_ZM_START_1_MASK             0x00FF  /* DSP2_ZM_START - [7:0] */
5058 #define WM5100_DSP2_ZM_START_1_SHIFT                 0  /* DSP2_ZM_START - [7:0] */
5059 #define WM5100_DSP2_ZM_START_1_WIDTH                 8  /* DSP2_ZM_START - [7:0] */
5062  * R28673 (0x7001) - DSP2 ZM 1
5064 #define WM5100_DSP2_ZM_START_MASK               0xFFFF  /* DSP2_ZM_START - [15:0] */
5065 #define WM5100_DSP2_ZM_START_SHIFT                   0  /* DSP2_ZM_START - [15:0] */
5066 #define WM5100_DSP2_ZM_START_WIDTH                  16  /* DSP2_ZM_START - [15:0] */
5069  * R28674 (0x7002) - DSP2 ZM 2
5071 #define WM5100_DSP2_ZM_1_1_MASK                 0x00FF  /* DSP2_ZM_1 - [7:0] */
5072 #define WM5100_DSP2_ZM_1_1_SHIFT                     0  /* DSP2_ZM_1 - [7:0] */
5073 #define WM5100_DSP2_ZM_1_1_WIDTH                     8  /* DSP2_ZM_1 - [7:0] */
5076  * R28675 (0x7003) - DSP2 ZM 3
5078 #define WM5100_DSP2_ZM_1_MASK                   0xFFFF  /* DSP2_ZM_1 - [15:0] */
5079 #define WM5100_DSP2_ZM_1_SHIFT                       0  /* DSP2_ZM_1 - [15:0] */
5080 #define WM5100_DSP2_ZM_1_WIDTH                      16  /* DSP2_ZM_1 - [15:0] */
5083  * R30716 (0x77FC) - DSP2 ZM 2044
5085 #define WM5100_DSP2_ZM_1022_1_MASK              0x00FF  /* DSP2_ZM_1022 - [7:0] */
5086 #define WM5100_DSP2_ZM_1022_1_SHIFT                  0  /* DSP2_ZM_1022 - [7:0] */
5087 #define WM5100_DSP2_ZM_1022_1_WIDTH                  8  /* DSP2_ZM_1022 - [7:0] */
5090  * R30717 (0x77FD) - DSP2 ZM 2045
5092 #define WM5100_DSP2_ZM_1022_MASK                0xFFFF  /* DSP2_ZM_1022 - [15:0] */
5093 #define WM5100_DSP2_ZM_1022_SHIFT                    0  /* DSP2_ZM_1022 - [15:0] */
5094 #define WM5100_DSP2_ZM_1022_WIDTH                   16  /* DSP2_ZM_1022 - [15:0] */
5097  * R30718 (0x77FE) - DSP2 ZM 2046
5099 #define WM5100_DSP2_ZM_END_1_MASK               0x00FF  /* DSP2_ZM_END - [7:0] */
5100 #define WM5100_DSP2_ZM_END_1_SHIFT                   0  /* DSP2_ZM_END - [7:0] */
5101 #define WM5100_DSP2_ZM_END_1_WIDTH                   8  /* DSP2_ZM_END - [7:0] */
5104  * R30719 (0x77FF) - DSP2 ZM 2047
5106 #define WM5100_DSP2_ZM_END_MASK                 0xFFFF  /* DSP2_ZM_END - [15:0] */
5107 #define WM5100_DSP2_ZM_END_SHIFT                     0  /* DSP2_ZM_END - [15:0] */
5108 #define WM5100_DSP2_ZM_END_WIDTH                    16  /* DSP2_ZM_END - [15:0] */
5111  * R32768 (0x8000) - DSP3 DM 0
5113 #define WM5100_DSP3_DM_START_1_MASK             0x00FF  /* DSP3_DM_START - [7:0] */
5114 #define WM5100_DSP3_DM_START_1_SHIFT                 0  /* DSP3_DM_START - [7:0] */
5115 #define WM5100_DSP3_DM_START_1_WIDTH                 8  /* DSP3_DM_START - [7:0] */
5118  * R32769 (0x8001) - DSP3 DM 1
5120 #define WM5100_DSP3_DM_START_MASK               0xFFFF  /* DSP3_DM_START - [15:0] */
5121 #define WM5100_DSP3_DM_START_SHIFT                   0  /* DSP3_DM_START - [15:0] */
5122 #define WM5100_DSP3_DM_START_WIDTH                  16  /* DSP3_DM_START - [15:0] */
5125  * R32770 (0x8002) - DSP3 DM 2
5127 #define WM5100_DSP3_DM_1_1_MASK                 0x00FF  /* DSP3_DM_1 - [7:0] */
5128 #define WM5100_DSP3_DM_1_1_SHIFT                     0  /* DSP3_DM_1 - [7:0] */
5129 #define WM5100_DSP3_DM_1_1_WIDTH                     8  /* DSP3_DM_1 - [7:0] */
5132  * R32771 (0x8003) - DSP3 DM 3
5134 #define WM5100_DSP3_DM_1_MASK                   0xFFFF  /* DSP3_DM_1 - [15:0] */
5135 #define WM5100_DSP3_DM_1_SHIFT                       0  /* DSP3_DM_1 - [15:0] */
5136 #define WM5100_DSP3_DM_1_WIDTH                      16  /* DSP3_DM_1 - [15:0] */
5139  * R33276 (0x81FC) - DSP3 DM 508
5141 #define WM5100_DSP3_DM_254_1_MASK               0x00FF  /* DSP3_DM_254 - [7:0] */
5142 #define WM5100_DSP3_DM_254_1_SHIFT                   0  /* DSP3_DM_254 - [7:0] */
5143 #define WM5100_DSP3_DM_254_1_WIDTH                   8  /* DSP3_DM_254 - [7:0] */
5146  * R33277 (0x81FD) - DSP3 DM 509
5148 #define WM5100_DSP3_DM_254_MASK                 0xFFFF  /* DSP3_DM_254 - [15:0] */
5149 #define WM5100_DSP3_DM_254_SHIFT                     0  /* DSP3_DM_254 - [15:0] */
5150 #define WM5100_DSP3_DM_254_WIDTH                    16  /* DSP3_DM_254 - [15:0] */
5153  * R33278 (0x81FE) - DSP3 DM 510
5155 #define WM5100_DSP3_DM_END_1_MASK               0x00FF  /* DSP3_DM_END - [7:0] */
5156 #define WM5100_DSP3_DM_END_1_SHIFT                   0  /* DSP3_DM_END - [7:0] */
5157 #define WM5100_DSP3_DM_END_1_WIDTH                   8  /* DSP3_DM_END - [7:0] */
5160  * R33279 (0x81FF) - DSP3 DM 511
5162 #define WM5100_DSP3_DM_END_MASK                 0xFFFF  /* DSP3_DM_END - [15:0] */
5163 #define WM5100_DSP3_DM_END_SHIFT                     0  /* DSP3_DM_END - [15:0] */
5164 #define WM5100_DSP3_DM_END_WIDTH                    16  /* DSP3_DM_END - [15:0] */
5167  * R34816 (0x8800) - DSP3 PM 0
5169 #define WM5100_DSP3_PM_START_2_MASK             0x00FF  /* DSP3_PM_START - [7:0] */
5170 #define WM5100_DSP3_PM_START_2_SHIFT                 0  /* DSP3_PM_START - [7:0] */
5171 #define WM5100_DSP3_PM_START_2_WIDTH                 8  /* DSP3_PM_START - [7:0] */
5174  * R34817 (0x8801) - DSP3 PM 1
5176 #define WM5100_DSP3_PM_START_1_MASK             0xFFFF  /* DSP3_PM_START - [15:0] */
5177 #define WM5100_DSP3_PM_START_1_SHIFT                 0  /* DSP3_PM_START - [15:0] */
5178 #define WM5100_DSP3_PM_START_1_WIDTH                16  /* DSP3_PM_START - [15:0] */
5181  * R34818 (0x8802) - DSP3 PM 2
5183 #define WM5100_DSP3_PM_START_MASK               0xFFFF  /* DSP3_PM_START - [15:0] */
5184 #define WM5100_DSP3_PM_START_SHIFT                   0  /* DSP3_PM_START - [15:0] */
5185 #define WM5100_DSP3_PM_START_WIDTH                  16  /* DSP3_PM_START - [15:0] */
5188  * R34819 (0x8803) - DSP3 PM 3
5190 #define WM5100_DSP3_PM_1_2_MASK                 0x00FF  /* DSP3_PM_1 - [7:0] */
5191 #define WM5100_DSP3_PM_1_2_SHIFT                     0  /* DSP3_PM_1 - [7:0] */
5192 #define WM5100_DSP3_PM_1_2_WIDTH                     8  /* DSP3_PM_1 - [7:0] */
5195  * R34820 (0x8804) - DSP3 PM 4
5197 #define WM5100_DSP3_PM_1_1_MASK                 0xFFFF  /* DSP3_PM_1 - [15:0] */
5198 #define WM5100_DSP3_PM_1_1_SHIFT                     0  /* DSP3_PM_1 - [15:0] */
5199 #define WM5100_DSP3_PM_1_1_WIDTH                    16  /* DSP3_PM_1 - [15:0] */
5202  * R34821 (0x8805) - DSP3 PM 5
5204 #define WM5100_DSP3_PM_1_MASK                   0xFFFF  /* DSP3_PM_1 - [15:0] */
5205 #define WM5100_DSP3_PM_1_SHIFT                       0  /* DSP3_PM_1 - [15:0] */
5206 #define WM5100_DSP3_PM_1_WIDTH                      16  /* DSP3_PM_1 - [15:0] */
5209  * R36346 (0x8DFA) - DSP3 PM 1530
5211 #define WM5100_DSP3_PM_510_2_MASK               0x00FF  /* DSP3_PM_510 - [7:0] */
5212 #define WM5100_DSP3_PM_510_2_SHIFT                   0  /* DSP3_PM_510 - [7:0] */
5213 #define WM5100_DSP3_PM_510_2_WIDTH                   8  /* DSP3_PM_510 - [7:0] */
5216  * R36347 (0x8DFB) - DSP3 PM 1531
5218 #define WM5100_DSP3_PM_510_1_MASK               0xFFFF  /* DSP3_PM_510 - [15:0] */
5219 #define WM5100_DSP3_PM_510_1_SHIFT                   0  /* DSP3_PM_510 - [15:0] */
5220 #define WM5100_DSP3_PM_510_1_WIDTH                  16  /* DSP3_PM_510 - [15:0] */
5223  * R36348 (0x8DFC) - DSP3 PM 1532
5225 #define WM5100_DSP3_PM_510_MASK                 0xFFFF  /* DSP3_PM_510 - [15:0] */
5226 #define WM5100_DSP3_PM_510_SHIFT                     0  /* DSP3_PM_510 - [15:0] */
5227 #define WM5100_DSP3_PM_510_WIDTH                    16  /* DSP3_PM_510 - [15:0] */
5230  * R36349 (0x8DFD) - DSP3 PM 1533
5232 #define WM5100_DSP3_PM_END_2_MASK               0x00FF  /* DSP3_PM_END - [7:0] */
5233 #define WM5100_DSP3_PM_END_2_SHIFT                   0  /* DSP3_PM_END - [7:0] */
5234 #define WM5100_DSP3_PM_END_2_WIDTH                   8  /* DSP3_PM_END - [7:0] */
5237  * R36350 (0x8DFE) - DSP3 PM 1534
5239 #define WM5100_DSP3_PM_END_1_MASK               0xFFFF  /* DSP3_PM_END - [15:0] */
5240 #define WM5100_DSP3_PM_END_1_SHIFT                   0  /* DSP3_PM_END - [15:0] */
5241 #define WM5100_DSP3_PM_END_1_WIDTH                  16  /* DSP3_PM_END - [15:0] */
5244  * R36351 (0x8DFF) - DSP3 PM 1535
5246 #define WM5100_DSP3_PM_END_MASK                 0xFFFF  /* DSP3_PM_END - [15:0] */
5247 #define WM5100_DSP3_PM_END_SHIFT                     0  /* DSP3_PM_END - [15:0] */
5248 #define WM5100_DSP3_PM_END_WIDTH                    16  /* DSP3_PM_END - [15:0] */
5251  * R36864 (0x9000) - DSP3 ZM 0
5253 #define WM5100_DSP3_ZM_START_1_MASK             0x00FF  /* DSP3_ZM_START - [7:0] */
5254 #define WM5100_DSP3_ZM_START_1_SHIFT                 0  /* DSP3_ZM_START - [7:0] */
5255 #define WM5100_DSP3_ZM_START_1_WIDTH                 8  /* DSP3_ZM_START - [7:0] */
5258  * R36865 (0x9001) - DSP3 ZM 1
5260 #define WM5100_DSP3_ZM_START_MASK               0xFFFF  /* DSP3_ZM_START - [15:0] */
5261 #define WM5100_DSP3_ZM_START_SHIFT                   0  /* DSP3_ZM_START - [15:0] */
5262 #define WM5100_DSP3_ZM_START_WIDTH                  16  /* DSP3_ZM_START - [15:0] */
5265  * R36866 (0x9002) - DSP3 ZM 2
5267 #define WM5100_DSP3_ZM_1_1_MASK                 0x00FF  /* DSP3_ZM_1 - [7:0] */
5268 #define WM5100_DSP3_ZM_1_1_SHIFT                     0  /* DSP3_ZM_1 - [7:0] */
5269 #define WM5100_DSP3_ZM_1_1_WIDTH                     8  /* DSP3_ZM_1 - [7:0] */
5272  * R36867 (0x9003) - DSP3 ZM 3
5274 #define WM5100_DSP3_ZM_1_MASK                   0xFFFF  /* DSP3_ZM_1 - [15:0] */
5275 #define WM5100_DSP3_ZM_1_SHIFT                       0  /* DSP3_ZM_1 - [15:0] */
5276 #define WM5100_DSP3_ZM_1_WIDTH                      16  /* DSP3_ZM_1 - [15:0] */
5279  * R38908 (0x97FC) - DSP3 ZM 2044
5281 #define WM5100_DSP3_ZM_1022_1_MASK              0x00FF  /* DSP3_ZM_1022 - [7:0] */
5282 #define WM5100_DSP3_ZM_1022_1_SHIFT                  0  /* DSP3_ZM_1022 - [7:0] */
5283 #define WM5100_DSP3_ZM_1022_1_WIDTH                  8  /* DSP3_ZM_1022 - [7:0] */
5286  * R38909 (0x97FD) - DSP3 ZM 2045
5288 #define WM5100_DSP3_ZM_1022_MASK                0xFFFF  /* DSP3_ZM_1022 - [15:0] */
5289 #define WM5100_DSP3_ZM_1022_SHIFT                    0  /* DSP3_ZM_1022 - [15:0] */
5290 #define WM5100_DSP3_ZM_1022_WIDTH                   16  /* DSP3_ZM_1022 - [15:0] */
5293  * R38910 (0x97FE) - DSP3 ZM 2046
5295 #define WM5100_DSP3_ZM_END_1_MASK               0x00FF  /* DSP3_ZM_END - [7:0] */
5296 #define WM5100_DSP3_ZM_END_1_SHIFT                   0  /* DSP3_ZM_END - [7:0] */
5297 #define WM5100_DSP3_ZM_END_1_WIDTH                   8  /* DSP3_ZM_END - [7:0] */
5300  * R38911 (0x97FF) - DSP3 ZM 2047
5302 #define WM5100_DSP3_ZM_END_MASK                 0xFFFF  /* DSP3_ZM_END - [15:0] */
5303 #define WM5100_DSP3_ZM_END_SHIFT                     0  /* DSP3_ZM_END - [15:0] */
5304 #define WM5100_DSP3_ZM_END_WIDTH                    16  /* DSP3_ZM_END - [15:0] */