Lines Matching +full:out +full:- +full:volume +full:- +full:limit
1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm2200.c -- WM2200 ALSA SoC Audio driver
163 { 0x000B, 0x0000 }, /* R11 - Tone Generator 1 */
164 { 0x0102, 0x0000 }, /* R258 - Clocking 3 */
165 { 0x0103, 0x0011 }, /* R259 - Clocking 4 */
166 { 0x0111, 0x0000 }, /* R273 - FLL Control 1 */
167 { 0x0112, 0x0000 }, /* R274 - FLL Control 2 */
168 { 0x0113, 0x0000 }, /* R275 - FLL Control 3 */
169 { 0x0114, 0x0000 }, /* R276 - FLL Control 4 */
170 { 0x0116, 0x0177 }, /* R278 - FLL Control 6 */
171 { 0x0117, 0x0004 }, /* R279 - FLL Control 7 */
172 { 0x0119, 0x0000 }, /* R281 - FLL EFS 1 */
173 { 0x011A, 0x0002 }, /* R282 - FLL EFS 2 */
174 { 0x0200, 0x0000 }, /* R512 - Mic Charge Pump 1 */
175 { 0x0201, 0x03FF }, /* R513 - Mic Charge Pump 2 */
176 { 0x0202, 0x9BDE }, /* R514 - DM Charge Pump 1 */
177 { 0x020C, 0x0000 }, /* R524 - Mic Bias Ctrl 1 */
178 { 0x020D, 0x0000 }, /* R525 - Mic Bias Ctrl 2 */
179 { 0x020F, 0x0000 }, /* R527 - Ear Piece Ctrl 1 */
180 { 0x0210, 0x0000 }, /* R528 - Ear Piece Ctrl 2 */
181 { 0x0301, 0x0000 }, /* R769 - Input Enables */
182 { 0x0302, 0x2240 }, /* R770 - IN1L Control */
183 { 0x0303, 0x0040 }, /* R771 - IN1R Control */
184 { 0x0304, 0x2240 }, /* R772 - IN2L Control */
185 { 0x0305, 0x0040 }, /* R773 - IN2R Control */
186 { 0x0306, 0x2240 }, /* R774 - IN3L Control */
187 { 0x0307, 0x0040 }, /* R775 - IN3R Control */
188 { 0x030A, 0x0000 }, /* R778 - RXANC_SRC */
189 { 0x030B, 0x0022 }, /* R779 - Input Volume Ramp */
190 { 0x030C, 0x0180 }, /* R780 - ADC Digital Volume 1L */
191 { 0x030D, 0x0180 }, /* R781 - ADC Digital Volume 1R */
192 { 0x030E, 0x0180 }, /* R782 - ADC Digital Volume 2L */
193 { 0x030F, 0x0180 }, /* R783 - ADC Digital Volume 2R */
194 { 0x0310, 0x0180 }, /* R784 - ADC Digital Volume 3L */
195 { 0x0311, 0x0180 }, /* R785 - ADC Digital Volume 3R */
196 { 0x0400, 0x0000 }, /* R1024 - Output Enables */
197 { 0x0401, 0x0000 }, /* R1025 - DAC Volume Limit 1L */
198 { 0x0402, 0x0000 }, /* R1026 - DAC Volume Limit 1R */
199 { 0x0403, 0x0000 }, /* R1027 - DAC Volume Limit 2L */
200 { 0x0404, 0x0000 }, /* R1028 - DAC Volume Limit 2R */
201 { 0x0409, 0x0000 }, /* R1033 - DAC AEC Control 1 */
202 { 0x040A, 0x0022 }, /* R1034 - Output Volume Ramp */
203 { 0x040B, 0x0180 }, /* R1035 - DAC Digital Volume 1L */
204 { 0x040C, 0x0180 }, /* R1036 - DAC Digital Volume 1R */
205 { 0x040D, 0x0180 }, /* R1037 - DAC Digital Volume 2L */
206 { 0x040E, 0x0180 }, /* R1038 - DAC Digital Volume 2R */
207 { 0x0417, 0x0069 }, /* R1047 - PDM 1 */
208 { 0x0418, 0x0000 }, /* R1048 - PDM 2 */
209 { 0x0500, 0x0000 }, /* R1280 - Audio IF 1_1 */
210 { 0x0501, 0x0008 }, /* R1281 - Audio IF 1_2 */
211 { 0x0502, 0x0000 }, /* R1282 - Audio IF 1_3 */
212 { 0x0503, 0x0000 }, /* R1283 - Audio IF 1_4 */
213 { 0x0504, 0x0000 }, /* R1284 - Audio IF 1_5 */
214 { 0x0505, 0x0001 }, /* R1285 - Audio IF 1_6 */
215 { 0x0506, 0x0001 }, /* R1286 - Audio IF 1_7 */
216 { 0x0507, 0x0000 }, /* R1287 - Audio IF 1_8 */
217 { 0x0508, 0x0000 }, /* R1288 - Audio IF 1_9 */
218 { 0x0509, 0x0000 }, /* R1289 - Audio IF 1_10 */
219 { 0x050A, 0x0000 }, /* R1290 - Audio IF 1_11 */
220 { 0x050B, 0x0000 }, /* R1291 - Audio IF 1_12 */
221 { 0x050C, 0x0000 }, /* R1292 - Audio IF 1_13 */
222 { 0x050D, 0x0000 }, /* R1293 - Audio IF 1_14 */
223 { 0x050E, 0x0000 }, /* R1294 - Audio IF 1_15 */
224 { 0x050F, 0x0000 }, /* R1295 - Audio IF 1_16 */
225 { 0x0510, 0x0000 }, /* R1296 - Audio IF 1_17 */
226 { 0x0511, 0x0000 }, /* R1297 - Audio IF 1_18 */
227 { 0x0512, 0x0000 }, /* R1298 - Audio IF 1_19 */
228 { 0x0513, 0x0000 }, /* R1299 - Audio IF 1_20 */
229 { 0x0514, 0x0000 }, /* R1300 - Audio IF 1_21 */
230 { 0x0515, 0x0001 }, /* R1301 - Audio IF 1_22 */
231 { 0x0600, 0x0000 }, /* R1536 - OUT1LMIX Input 1 Source */
232 { 0x0601, 0x0080 }, /* R1537 - OUT1LMIX Input 1 Volume */
233 { 0x0602, 0x0000 }, /* R1538 - OUT1LMIX Input 2 Source */
234 { 0x0603, 0x0080 }, /* R1539 - OUT1LMIX Input 2 Volume */
235 { 0x0604, 0x0000 }, /* R1540 - OUT1LMIX Input 3 Source */
236 { 0x0605, 0x0080 }, /* R1541 - OUT1LMIX Input 3 Volume */
237 { 0x0606, 0x0000 }, /* R1542 - OUT1LMIX Input 4 Source */
238 { 0x0607, 0x0080 }, /* R1543 - OUT1LMIX Input 4 Volume */
239 { 0x0608, 0x0000 }, /* R1544 - OUT1RMIX Input 1 Source */
240 { 0x0609, 0x0080 }, /* R1545 - OUT1RMIX Input 1 Volume */
241 { 0x060A, 0x0000 }, /* R1546 - OUT1RMIX Input 2 Source */
242 { 0x060B, 0x0080 }, /* R1547 - OUT1RMIX Input 2 Volume */
243 { 0x060C, 0x0000 }, /* R1548 - OUT1RMIX Input 3 Source */
244 { 0x060D, 0x0080 }, /* R1549 - OUT1RMIX Input 3 Volume */
245 { 0x060E, 0x0000 }, /* R1550 - OUT1RMIX Input 4 Source */
246 { 0x060F, 0x0080 }, /* R1551 - OUT1RMIX Input 4 Volume */
247 { 0x0610, 0x0000 }, /* R1552 - OUT2LMIX Input 1 Source */
248 { 0x0611, 0x0080 }, /* R1553 - OUT2LMIX Input 1 Volume */
249 { 0x0612, 0x0000 }, /* R1554 - OUT2LMIX Input 2 Source */
250 { 0x0613, 0x0080 }, /* R1555 - OUT2LMIX Input 2 Volume */
251 { 0x0614, 0x0000 }, /* R1556 - OUT2LMIX Input 3 Source */
252 { 0x0615, 0x0080 }, /* R1557 - OUT2LMIX Input 3 Volume */
253 { 0x0616, 0x0000 }, /* R1558 - OUT2LMIX Input 4 Source */
254 { 0x0617, 0x0080 }, /* R1559 - OUT2LMIX Input 4 Volume */
255 { 0x0618, 0x0000 }, /* R1560 - OUT2RMIX Input 1 Source */
256 { 0x0619, 0x0080 }, /* R1561 - OUT2RMIX Input 1 Volume */
257 { 0x061A, 0x0000 }, /* R1562 - OUT2RMIX Input 2 Source */
258 { 0x061B, 0x0080 }, /* R1563 - OUT2RMIX Input 2 Volume */
259 { 0x061C, 0x0000 }, /* R1564 - OUT2RMIX Input 3 Source */
260 { 0x061D, 0x0080 }, /* R1565 - OUT2RMIX Input 3 Volume */
261 { 0x061E, 0x0000 }, /* R1566 - OUT2RMIX Input 4 Source */
262 { 0x061F, 0x0080 }, /* R1567 - OUT2RMIX Input 4 Volume */
263 { 0x0620, 0x0000 }, /* R1568 - AIF1TX1MIX Input 1 Source */
264 { 0x0621, 0x0080 }, /* R1569 - AIF1TX1MIX Input 1 Volume */
265 { 0x0622, 0x0000 }, /* R1570 - AIF1TX1MIX Input 2 Source */
266 { 0x0623, 0x0080 }, /* R1571 - AIF1TX1MIX Input 2 Volume */
267 { 0x0624, 0x0000 }, /* R1572 - AIF1TX1MIX Input 3 Source */
268 { 0x0625, 0x0080 }, /* R1573 - AIF1TX1MIX Input 3 Volume */
269 { 0x0626, 0x0000 }, /* R1574 - AIF1TX1MIX Input 4 Source */
270 { 0x0627, 0x0080 }, /* R1575 - AIF1TX1MIX Input 4 Volume */
271 { 0x0628, 0x0000 }, /* R1576 - AIF1TX2MIX Input 1 Source */
272 { 0x0629, 0x0080 }, /* R1577 - AIF1TX2MIX Input 1 Volume */
273 { 0x062A, 0x0000 }, /* R1578 - AIF1TX2MIX Input 2 Source */
274 { 0x062B, 0x0080 }, /* R1579 - AIF1TX2MIX Input 2 Volume */
275 { 0x062C, 0x0000 }, /* R1580 - AIF1TX2MIX Input 3 Source */
276 { 0x062D, 0x0080 }, /* R1581 - AIF1TX2MIX Input 3 Volume */
277 { 0x062E, 0x0000 }, /* R1582 - AIF1TX2MIX Input 4 Source */
278 { 0x062F, 0x0080 }, /* R1583 - AIF1TX2MIX Input 4 Volume */
279 { 0x0630, 0x0000 }, /* R1584 - AIF1TX3MIX Input 1 Source */
280 { 0x0631, 0x0080 }, /* R1585 - AIF1TX3MIX Input 1 Volume */
281 { 0x0632, 0x0000 }, /* R1586 - AIF1TX3MIX Input 2 Source */
282 { 0x0633, 0x0080 }, /* R1587 - AIF1TX3MIX Input 2 Volume */
283 { 0x0634, 0x0000 }, /* R1588 - AIF1TX3MIX Input 3 Source */
284 { 0x0635, 0x0080 }, /* R1589 - AIF1TX3MIX Input 3 Volume */
285 { 0x0636, 0x0000 }, /* R1590 - AIF1TX3MIX Input 4 Source */
286 { 0x0637, 0x0080 }, /* R1591 - AIF1TX3MIX Input 4 Volume */
287 { 0x0638, 0x0000 }, /* R1592 - AIF1TX4MIX Input 1 Source */
288 { 0x0639, 0x0080 }, /* R1593 - AIF1TX4MIX Input 1 Volume */
289 { 0x063A, 0x0000 }, /* R1594 - AIF1TX4MIX Input 2 Source */
290 { 0x063B, 0x0080 }, /* R1595 - AIF1TX4MIX Input 2 Volume */
291 { 0x063C, 0x0000 }, /* R1596 - AIF1TX4MIX Input 3 Source */
292 { 0x063D, 0x0080 }, /* R1597 - AIF1TX4MIX Input 3 Volume */
293 { 0x063E, 0x0000 }, /* R1598 - AIF1TX4MIX Input 4 Source */
294 { 0x063F, 0x0080 }, /* R1599 - AIF1TX4MIX Input 4 Volume */
295 { 0x0640, 0x0000 }, /* R1600 - AIF1TX5MIX Input 1 Source */
296 { 0x0641, 0x0080 }, /* R1601 - AIF1TX5MIX Input 1 Volume */
297 { 0x0642, 0x0000 }, /* R1602 - AIF1TX5MIX Input 2 Source */
298 { 0x0643, 0x0080 }, /* R1603 - AIF1TX5MIX Input 2 Volume */
299 { 0x0644, 0x0000 }, /* R1604 - AIF1TX5MIX Input 3 Source */
300 { 0x0645, 0x0080 }, /* R1605 - AIF1TX5MIX Input 3 Volume */
301 { 0x0646, 0x0000 }, /* R1606 - AIF1TX5MIX Input 4 Source */
302 { 0x0647, 0x0080 }, /* R1607 - AIF1TX5MIX Input 4 Volume */
303 { 0x0648, 0x0000 }, /* R1608 - AIF1TX6MIX Input 1 Source */
304 { 0x0649, 0x0080 }, /* R1609 - AIF1TX6MIX Input 1 Volume */
305 { 0x064A, 0x0000 }, /* R1610 - AIF1TX6MIX Input 2 Source */
306 { 0x064B, 0x0080 }, /* R1611 - AIF1TX6MIX Input 2 Volume */
307 { 0x064C, 0x0000 }, /* R1612 - AIF1TX6MIX Input 3 Source */
308 { 0x064D, 0x0080 }, /* R1613 - AIF1TX6MIX Input 3 Volume */
309 { 0x064E, 0x0000 }, /* R1614 - AIF1TX6MIX Input 4 Source */
310 { 0x064F, 0x0080 }, /* R1615 - AIF1TX6MIX Input 4 Volume */
311 { 0x0650, 0x0000 }, /* R1616 - EQLMIX Input 1 Source */
312 { 0x0651, 0x0080 }, /* R1617 - EQLMIX Input 1 Volume */
313 { 0x0652, 0x0000 }, /* R1618 - EQLMIX Input 2 Source */
314 { 0x0653, 0x0080 }, /* R1619 - EQLMIX Input 2 Volume */
315 { 0x0654, 0x0000 }, /* R1620 - EQLMIX Input 3 Source */
316 { 0x0655, 0x0080 }, /* R1621 - EQLMIX Input 3 Volume */
317 { 0x0656, 0x0000 }, /* R1622 - EQLMIX Input 4 Source */
318 { 0x0657, 0x0080 }, /* R1623 - EQLMIX Input 4 Volume */
319 { 0x0658, 0x0000 }, /* R1624 - EQRMIX Input 1 Source */
320 { 0x0659, 0x0080 }, /* R1625 - EQRMIX Input 1 Volume */
321 { 0x065A, 0x0000 }, /* R1626 - EQRMIX Input 2 Source */
322 { 0x065B, 0x0080 }, /* R1627 - EQRMIX Input 2 Volume */
323 { 0x065C, 0x0000 }, /* R1628 - EQRMIX Input 3 Source */
324 { 0x065D, 0x0080 }, /* R1629 - EQRMIX Input 3 Volume */
325 { 0x065E, 0x0000 }, /* R1630 - EQRMIX Input 4 Source */
326 { 0x065F, 0x0080 }, /* R1631 - EQRMIX Input 4 Volume */
327 { 0x0660, 0x0000 }, /* R1632 - LHPF1MIX Input 1 Source */
328 { 0x0661, 0x0080 }, /* R1633 - LHPF1MIX Input 1 Volume */
329 { 0x0662, 0x0000 }, /* R1634 - LHPF1MIX Input 2 Source */
330 { 0x0663, 0x0080 }, /* R1635 - LHPF1MIX Input 2 Volume */
331 { 0x0664, 0x0000 }, /* R1636 - LHPF1MIX Input 3 Source */
332 { 0x0665, 0x0080 }, /* R1637 - LHPF1MIX Input 3 Volume */
333 { 0x0666, 0x0000 }, /* R1638 - LHPF1MIX Input 4 Source */
334 { 0x0667, 0x0080 }, /* R1639 - LHPF1MIX Input 4 Volume */
335 { 0x0668, 0x0000 }, /* R1640 - LHPF2MIX Input 1 Source */
336 { 0x0669, 0x0080 }, /* R1641 - LHPF2MIX Input 1 Volume */
337 { 0x066A, 0x0000 }, /* R1642 - LHPF2MIX Input 2 Source */
338 { 0x066B, 0x0080 }, /* R1643 - LHPF2MIX Input 2 Volume */
339 { 0x066C, 0x0000 }, /* R1644 - LHPF2MIX Input 3 Source */
340 { 0x066D, 0x0080 }, /* R1645 - LHPF2MIX Input 3 Volume */
341 { 0x066E, 0x0000 }, /* R1646 - LHPF2MIX Input 4 Source */
342 { 0x066F, 0x0080 }, /* R1647 - LHPF2MIX Input 4 Volume */
343 { 0x0670, 0x0000 }, /* R1648 - DSP1LMIX Input 1 Source */
344 { 0x0671, 0x0080 }, /* R1649 - DSP1LMIX Input 1 Volume */
345 { 0x0672, 0x0000 }, /* R1650 - DSP1LMIX Input 2 Source */
346 { 0x0673, 0x0080 }, /* R1651 - DSP1LMIX Input 2 Volume */
347 { 0x0674, 0x0000 }, /* R1652 - DSP1LMIX Input 3 Source */
348 { 0x0675, 0x0080 }, /* R1653 - DSP1LMIX Input 3 Volume */
349 { 0x0676, 0x0000 }, /* R1654 - DSP1LMIX Input 4 Source */
350 { 0x0677, 0x0080 }, /* R1655 - DSP1LMIX Input 4 Volume */
351 { 0x0678, 0x0000 }, /* R1656 - DSP1RMIX Input 1 Source */
352 { 0x0679, 0x0080 }, /* R1657 - DSP1RMIX Input 1 Volume */
353 { 0x067A, 0x0000 }, /* R1658 - DSP1RMIX Input 2 Source */
354 { 0x067B, 0x0080 }, /* R1659 - DSP1RMIX Input 2 Volume */
355 { 0x067C, 0x0000 }, /* R1660 - DSP1RMIX Input 3 Source */
356 { 0x067D, 0x0080 }, /* R1661 - DSP1RMIX Input 3 Volume */
357 { 0x067E, 0x0000 }, /* R1662 - DSP1RMIX Input 4 Source */
358 { 0x067F, 0x0080 }, /* R1663 - DSP1RMIX Input 4 Volume */
359 { 0x0680, 0x0000 }, /* R1664 - DSP1AUX1MIX Input 1 Source */
360 { 0x0681, 0x0000 }, /* R1665 - DSP1AUX2MIX Input 1 Source */
361 { 0x0682, 0x0000 }, /* R1666 - DSP1AUX3MIX Input 1 Source */
362 { 0x0683, 0x0000 }, /* R1667 - DSP1AUX4MIX Input 1 Source */
363 { 0x0684, 0x0000 }, /* R1668 - DSP1AUX5MIX Input 1 Source */
364 { 0x0685, 0x0000 }, /* R1669 - DSP1AUX6MIX Input 1 Source */
365 { 0x0686, 0x0000 }, /* R1670 - DSP2LMIX Input 1 Source */
366 { 0x0687, 0x0080 }, /* R1671 - DSP2LMIX Input 1 Volume */
367 { 0x0688, 0x0000 }, /* R1672 - DSP2LMIX Input 2 Source */
368 { 0x0689, 0x0080 }, /* R1673 - DSP2LMIX Input 2 Volume */
369 { 0x068A, 0x0000 }, /* R1674 - DSP2LMIX Input 3 Source */
370 { 0x068B, 0x0080 }, /* R1675 - DSP2LMIX Input 3 Volume */
371 { 0x068C, 0x0000 }, /* R1676 - DSP2LMIX Input 4 Source */
372 { 0x068D, 0x0080 }, /* R1677 - DSP2LMIX Input 4 Volume */
373 { 0x068E, 0x0000 }, /* R1678 - DSP2RMIX Input 1 Source */
374 { 0x068F, 0x0080 }, /* R1679 - DSP2RMIX Input 1 Volume */
375 { 0x0690, 0x0000 }, /* R1680 - DSP2RMIX Input 2 Source */
376 { 0x0691, 0x0080 }, /* R1681 - DSP2RMIX Input 2 Volume */
377 { 0x0692, 0x0000 }, /* R1682 - DSP2RMIX Input 3 Source */
378 { 0x0693, 0x0080 }, /* R1683 - DSP2RMIX Input 3 Volume */
379 { 0x0694, 0x0000 }, /* R1684 - DSP2RMIX Input 4 Source */
380 { 0x0695, 0x0080 }, /* R1685 - DSP2RMIX Input 4 Volume */
381 { 0x0696, 0x0000 }, /* R1686 - DSP2AUX1MIX Input 1 Source */
382 { 0x0697, 0x0000 }, /* R1687 - DSP2AUX2MIX Input 1 Source */
383 { 0x0698, 0x0000 }, /* R1688 - DSP2AUX3MIX Input 1 Source */
384 { 0x0699, 0x0000 }, /* R1689 - DSP2AUX4MIX Input 1 Source */
385 { 0x069A, 0x0000 }, /* R1690 - DSP2AUX5MIX Input 1 Source */
386 { 0x069B, 0x0000 }, /* R1691 - DSP2AUX6MIX Input 1 Source */
387 { 0x0700, 0xA101 }, /* R1792 - GPIO CTRL 1 */
388 { 0x0701, 0xA101 }, /* R1793 - GPIO CTRL 2 */
389 { 0x0702, 0xA101 }, /* R1794 - GPIO CTRL 3 */
390 { 0x0703, 0xA101 }, /* R1795 - GPIO CTRL 4 */
391 { 0x0709, 0x0000 }, /* R1801 - Misc Pad Ctrl 1 */
392 { 0x0801, 0x00FF }, /* R2049 - Interrupt Status 1 Mask */
393 { 0x0804, 0xFFFF }, /* R2052 - Interrupt Status 2 Mask */
394 { 0x0808, 0x0000 }, /* R2056 - Interrupt Control */
395 { 0x0900, 0x0000 }, /* R2304 - EQL_1 */
396 { 0x0901, 0x0000 }, /* R2305 - EQL_2 */
397 { 0x0902, 0x0000 }, /* R2306 - EQL_3 */
398 { 0x0903, 0x0000 }, /* R2307 - EQL_4 */
399 { 0x0904, 0x0000 }, /* R2308 - EQL_5 */
400 { 0x0905, 0x0000 }, /* R2309 - EQL_6 */
401 { 0x0906, 0x0000 }, /* R2310 - EQL_7 */
402 { 0x0907, 0x0000 }, /* R2311 - EQL_8 */
403 { 0x0908, 0x0000 }, /* R2312 - EQL_9 */
404 { 0x0909, 0x0000 }, /* R2313 - EQL_10 */
405 { 0x090A, 0x0000 }, /* R2314 - EQL_11 */
406 { 0x090B, 0x0000 }, /* R2315 - EQL_12 */
407 { 0x090C, 0x0000 }, /* R2316 - EQL_13 */
408 { 0x090D, 0x0000 }, /* R2317 - EQL_14 */
409 { 0x090E, 0x0000 }, /* R2318 - EQL_15 */
410 { 0x090F, 0x0000 }, /* R2319 - EQL_16 */
411 { 0x0910, 0x0000 }, /* R2320 - EQL_17 */
412 { 0x0911, 0x0000 }, /* R2321 - EQL_18 */
413 { 0x0912, 0x0000 }, /* R2322 - EQL_19 */
414 { 0x0913, 0x0000 }, /* R2323 - EQL_20 */
415 { 0x0916, 0x0000 }, /* R2326 - EQR_1 */
416 { 0x0917, 0x0000 }, /* R2327 - EQR_2 */
417 { 0x0918, 0x0000 }, /* R2328 - EQR_3 */
418 { 0x0919, 0x0000 }, /* R2329 - EQR_4 */
419 { 0x091A, 0x0000 }, /* R2330 - EQR_5 */
420 { 0x091B, 0x0000 }, /* R2331 - EQR_6 */
421 { 0x091C, 0x0000 }, /* R2332 - EQR_7 */
422 { 0x091D, 0x0000 }, /* R2333 - EQR_8 */
423 { 0x091E, 0x0000 }, /* R2334 - EQR_9 */
424 { 0x091F, 0x0000 }, /* R2335 - EQR_10 */
425 { 0x0920, 0x0000 }, /* R2336 - EQR_11 */
426 { 0x0921, 0x0000 }, /* R2337 - EQR_12 */
427 { 0x0922, 0x0000 }, /* R2338 - EQR_13 */
428 { 0x0923, 0x0000 }, /* R2339 - EQR_14 */
429 { 0x0924, 0x0000 }, /* R2340 - EQR_15 */
430 { 0x0925, 0x0000 }, /* R2341 - EQR_16 */
431 { 0x0926, 0x0000 }, /* R2342 - EQR_17 */
432 { 0x0927, 0x0000 }, /* R2343 - EQR_18 */
433 { 0x0928, 0x0000 }, /* R2344 - EQR_19 */
434 { 0x0929, 0x0000 }, /* R2345 - EQR_20 */
435 { 0x093E, 0x0000 }, /* R2366 - HPLPF1_1 */
436 { 0x093F, 0x0000 }, /* R2367 - HPLPF1_2 */
437 { 0x0942, 0x0000 }, /* R2370 - HPLPF2_1 */
438 { 0x0943, 0x0000 }, /* R2371 - HPLPF2_2 */
439 { 0x0A00, 0x0000 }, /* R2560 - DSP1 Control 1 */
440 { 0x0A02, 0x0000 }, /* R2562 - DSP1 Control 2 */
441 { 0x0A03, 0x0000 }, /* R2563 - DSP1 Control 3 */
442 { 0x0A04, 0x0000 }, /* R2564 - DSP1 Control 4 */
443 { 0x0A06, 0x0000 }, /* R2566 - DSP1 Control 5 */
444 { 0x0A07, 0x0000 }, /* R2567 - DSP1 Control 6 */
445 { 0x0A08, 0x0000 }, /* R2568 - DSP1 Control 7 */
446 { 0x0A09, 0x0000 }, /* R2569 - DSP1 Control 8 */
447 { 0x0A0A, 0x0000 }, /* R2570 - DSP1 Control 9 */
448 { 0x0A0B, 0x0000 }, /* R2571 - DSP1 Control 10 */
449 { 0x0A0C, 0x0000 }, /* R2572 - DSP1 Control 11 */
450 { 0x0A0D, 0x0000 }, /* R2573 - DSP1 Control 12 */
451 { 0x0A0F, 0x0000 }, /* R2575 - DSP1 Control 13 */
452 { 0x0A10, 0x0000 }, /* R2576 - DSP1 Control 14 */
453 { 0x0A11, 0x0000 }, /* R2577 - DSP1 Control 15 */
454 { 0x0A12, 0x0000 }, /* R2578 - DSP1 Control 16 */
455 { 0x0A13, 0x0000 }, /* R2579 - DSP1 Control 17 */
456 { 0x0A14, 0x0000 }, /* R2580 - DSP1 Control 18 */
457 { 0x0A16, 0x0000 }, /* R2582 - DSP1 Control 19 */
458 { 0x0A17, 0x0000 }, /* R2583 - DSP1 Control 20 */
459 { 0x0A18, 0x0000 }, /* R2584 - DSP1 Control 21 */
460 { 0x0A1A, 0x1800 }, /* R2586 - DSP1 Control 22 */
461 { 0x0A1B, 0x1000 }, /* R2587 - DSP1 Control 23 */
462 { 0x0A1C, 0x0400 }, /* R2588 - DSP1 Control 24 */
463 { 0x0A1E, 0x0000 }, /* R2590 - DSP1 Control 25 */
464 { 0x0A20, 0x0000 }, /* R2592 - DSP1 Control 26 */
465 { 0x0A21, 0x0000 }, /* R2593 - DSP1 Control 27 */
466 { 0x0A22, 0x0000 }, /* R2594 - DSP1 Control 28 */
467 { 0x0A23, 0x0000 }, /* R2595 - DSP1 Control 29 */
468 { 0x0A24, 0x0000 }, /* R2596 - DSP1 Control 30 */
469 { 0x0A26, 0x0000 }, /* R2598 - DSP1 Control 31 */
470 { 0x0B00, 0x0000 }, /* R2816 - DSP2 Control 1 */
471 { 0x0B02, 0x0000 }, /* R2818 - DSP2 Control 2 */
472 { 0x0B03, 0x0000 }, /* R2819 - DSP2 Control 3 */
473 { 0x0B04, 0x0000 }, /* R2820 - DSP2 Control 4 */
474 { 0x0B06, 0x0000 }, /* R2822 - DSP2 Control 5 */
475 { 0x0B07, 0x0000 }, /* R2823 - DSP2 Control 6 */
476 { 0x0B08, 0x0000 }, /* R2824 - DSP2 Control 7 */
477 { 0x0B09, 0x0000 }, /* R2825 - DSP2 Control 8 */
478 { 0x0B0A, 0x0000 }, /* R2826 - DSP2 Control 9 */
479 { 0x0B0B, 0x0000 }, /* R2827 - DSP2 Control 10 */
480 { 0x0B0C, 0x0000 }, /* R2828 - DSP2 Control 11 */
481 { 0x0B0D, 0x0000 }, /* R2829 - DSP2 Control 12 */
482 { 0x0B0F, 0x0000 }, /* R2831 - DSP2 Control 13 */
483 { 0x0B10, 0x0000 }, /* R2832 - DSP2 Control 14 */
484 { 0x0B11, 0x0000 }, /* R2833 - DSP2 Control 15 */
485 { 0x0B12, 0x0000 }, /* R2834 - DSP2 Control 16 */
486 { 0x0B13, 0x0000 }, /* R2835 - DSP2 Control 17 */
487 { 0x0B14, 0x0000 }, /* R2836 - DSP2 Control 18 */
488 { 0x0B16, 0x0000 }, /* R2838 - DSP2 Control 19 */
489 { 0x0B17, 0x0000 }, /* R2839 - DSP2 Control 20 */
490 { 0x0B18, 0x0000 }, /* R2840 - DSP2 Control 21 */
491 { 0x0B1A, 0x0800 }, /* R2842 - DSP2 Control 22 */
492 { 0x0B1B, 0x1000 }, /* R2843 - DSP2 Control 23 */
493 { 0x0B1C, 0x0400 }, /* R2844 - DSP2 Control 24 */
494 { 0x0B1E, 0x0000 }, /* R2846 - DSP2 Control 25 */
495 { 0x0B20, 0x0000 }, /* R2848 - DSP2 Control 26 */
496 { 0x0B21, 0x0000 }, /* R2849 - DSP2 Control 27 */
497 { 0x0B22, 0x0000 }, /* R2850 - DSP2 Control 28 */
498 { 0x0B23, 0x0000 }, /* R2851 - DSP2 Control 29 */
499 { 0x0B24, 0x0000 }, /* R2852 - DSP2 Control 30 */
500 { 0x0B26, 0x0000 }, /* R2854 - DSP2 Control 31 */
980 if (wm2200->reset) { in wm2200_reset()
982 gpiod_set_value_cansleep(wm2200->reset, 1); in wm2200_reset()
983 gpiod_set_value_cansleep(wm2200->reset, 0); in wm2200_reset()
987 return regmap_write(wm2200->regmap, WM2200_SOFTWARE_RESET, in wm2200_reset()
992 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
993 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
994 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
1065 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
1067 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
1069 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
1071 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
1123 SOC_DOUBLE_R_TLV("IN1 Volume", WM2200_IN1L_CONTROL, WM2200_IN1R_CONTROL,
1125 SOC_DOUBLE_R_TLV("IN2 Volume", WM2200_IN2L_CONTROL, WM2200_IN2R_CONTROL,
1127 SOC_DOUBLE_R_TLV("IN3 Volume", WM2200_IN3L_CONTROL, WM2200_IN3R_CONTROL,
1137 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L,
1140 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_2L,
1143 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L,
1160 SOC_DOUBLE_R_TLV("OUT1 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_1L,
1163 SOC_DOUBLE_R_TLV("OUT1 Volume", WM2200_DAC_VOLUME_LIMIT_1L,
1169 SOC_DOUBLE_R_TLV("OUT2 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_2L,
1552 wm2200->component = component; in wm2200_probe()
1559 struct snd_soc_component *component = dai->component; in wm2200_set_fmt()
1573 dev_err(component->dev, "Unsupported DAI format %d\n", in wm2200_set_fmt()
1575 return -EINVAL; in wm2200_set_fmt()
1592 dev_err(component->dev, "Unsupported master mode %d\n", in wm2200_set_fmt()
1594 return -EINVAL; in wm2200_set_fmt()
1611 return -EINVAL; in wm2200_set_fmt()
1691 struct snd_soc_component *component = dai->component; in wm2200_hw_params()
1704 dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n", in wm2200_hw_params()
1712 if (!wm2200->sysclk) { in wm2200_hw_params()
1713 dev_err(component->dev, "SYSCLK has no rate set\n"); in wm2200_hw_params()
1714 return -EINVAL; in wm2200_hw_params()
1721 dev_err(component->dev, "Unsupported sample rate: %dHz\n", in wm2200_hw_params()
1723 return -EINVAL; in wm2200_hw_params()
1727 dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n", in wm2200_hw_params()
1728 bclk, wm2200->sysclk); in wm2200_hw_params()
1730 if (wm2200->sysclk % 4000) in wm2200_hw_params()
1739 dev_err(component->dev, in wm2200_hw_params()
1741 bclk, wm2200->sysclk); in wm2200_hw_params()
1742 return -EINVAL; in wm2200_hw_params()
1746 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); in wm2200_hw_params()
1751 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk); in wm2200_hw_params()
1752 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || in wm2200_hw_params()
1753 wm2200->symmetric_rates) in wm2200_hw_params()
1761 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in wm2200_hw_params()
1787 dev_err(component->dev, "Unknown clock %d\n", clk_id); in wm2200_set_sysclk()
1788 return -EINVAL; in wm2200_set_sysclk()
1798 dev_err(component->dev, "Invalid source %d\n", source); in wm2200_set_sysclk()
1799 return -EINVAL; in wm2200_set_sysclk()
1808 dev_err(component->dev, "Invalid clock rate: %d\n", freq); in wm2200_set_sysclk()
1809 return -EINVAL; in wm2200_set_sysclk()
1820 wm2200->sysclk = freq; in wm2200_set_sysclk()
1857 fll_div->fll_refclk_div = 0; in fll_factors()
1860 fll_div->fll_refclk_div++; in fll_factors()
1865 return -EINVAL; in fll_factors()
1874 /* Fvco should be 90-100MHz; don't check the upper bound */ in fll_factors()
1881 return -EINVAL; in fll_factors()
1885 fll_div->fll_outdiv = div - 1; in fll_factors()
1889 /* Find an appropraite FLL_FRATIO and factor it out of the target */ in fll_factors()
1892 fll_div->fll_fratio = fll_fratios[i].fll_fratio; in fll_factors()
1899 return -EINVAL; in fll_factors()
1902 fll_div->n = target / (fratio * Fref); in fll_factors()
1905 fll_div->theta = 0; in fll_factors()
1906 fll_div->lambda = 0; in fll_factors()
1910 fll_div->theta = (target - (fll_div->n * fratio * Fref)) in fll_factors()
1912 fll_div->lambda = (fratio * Fref) / gcd_fll; in fll_factors()
1916 fll_div->n, fll_div->theta, fll_div->lambda); in fll_factors()
1918 fll_div->fll_fratio, fratio, fll_div->fll_outdiv, in fll_factors()
1919 fll_div->fll_refclk_div); in fll_factors()
1927 struct i2c_client *i2c = to_i2c_client(component->dev); in wm2200_set_fll()
1934 dev_dbg(component->dev, "FLL disabled"); in wm2200_set_fll()
1936 if (wm2200->fll_fout) in wm2200_set_fll()
1937 pm_runtime_put(component->dev); in wm2200_set_fll()
1939 wm2200->fll_fout = 0; in wm2200_set_fll()
1951 dev_err(component->dev, "Invalid FLL source %d\n", source); in wm2200_set_fll()
1952 return -EINVAL; in wm2200_set_fll()
1993 try_wait_for_completion(&wm2200->fll_lock); in wm2200_set_fll()
1995 pm_runtime_get_sync(component->dev); in wm2200_set_fll()
2000 if (i2c->irq) in wm2200_set_fll()
2010 if (i2c->irq) { in wm2200_set_fll()
2012 &wm2200->fll_lock, in wm2200_set_fll()
2023 dev_err(component->dev, in wm2200_set_fll()
2032 dev_err(component->dev, "FLL lock timed out\n"); in wm2200_set_fll()
2033 pm_runtime_put(component->dev); in wm2200_set_fll()
2034 return -ETIMEDOUT; in wm2200_set_fll()
2037 wm2200->fll_src = source; in wm2200_set_fll()
2038 wm2200->fll_fref = Fref; in wm2200_set_fll()
2039 wm2200->fll_fout = Fout; in wm2200_set_fll()
2041 dev_dbg(component->dev, "FLL running %dHz->%dHz\n", Fref, Fout); in wm2200_set_fll()
2048 struct snd_soc_component *component = dai->component; in wm2200_dai_probe()
2056 wm2200->symmetric_rates = true; in wm2200_dai_probe()
2060 dev_err(component->dev, "Failed to read GPIO 1 config: %d\n", ret); in wm2200_dai_probe()
2118 ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, &val); in wm2200_irq()
2120 dev_err(wm2200->dev, "Failed to read IRQ status: %d\n", ret); in wm2200_irq()
2124 ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2_MASK, in wm2200_irq()
2127 dev_warn(wm2200->dev, "Failed to read IRQ mask: %d\n", ret); in wm2200_irq()
2134 dev_dbg(wm2200->dev, "FLL locked\n"); in wm2200_irq()
2135 complete(&wm2200->fll_lock); in wm2200_irq()
2139 regmap_write(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, val); in wm2200_irq()
2183 struct wm2200_pdata *pdata = dev_get_platdata(&i2c->dev); in wm2200_i2c_probe()
2189 wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv), in wm2200_i2c_probe()
2192 return -ENOMEM; in wm2200_i2c_probe()
2194 wm2200->dev = &i2c->dev; in wm2200_i2c_probe()
2195 init_completion(&wm2200->fll_lock); in wm2200_i2c_probe()
2197 wm2200->regmap = devm_regmap_init_i2c(i2c, &wm2200_regmap); in wm2200_i2c_probe()
2198 if (IS_ERR(wm2200->regmap)) { in wm2200_i2c_probe()
2199 ret = PTR_ERR(wm2200->regmap); in wm2200_i2c_probe()
2200 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in wm2200_i2c_probe()
2206 wm2200->dsp[i].cs_dsp.type = WMFW_ADSP1; in wm2200_i2c_probe()
2207 wm2200->dsp[i].part = "wm2200"; in wm2200_i2c_probe()
2208 wm2200->dsp[i].cs_dsp.num = i + 1; in wm2200_i2c_probe()
2209 wm2200->dsp[i].cs_dsp.dev = &i2c->dev; in wm2200_i2c_probe()
2210 wm2200->dsp[i].cs_dsp.regmap = wm2200->regmap; in wm2200_i2c_probe()
2211 wm2200->dsp[i].cs_dsp.sysclk_reg = WM2200_CLOCKING_3; in wm2200_i2c_probe()
2212 wm2200->dsp[i].cs_dsp.sysclk_mask = WM2200_SYSCLK_FREQ_MASK; in wm2200_i2c_probe()
2213 wm2200->dsp[i].cs_dsp.sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT; in wm2200_i2c_probe()
2216 wm2200->dsp[0].cs_dsp.base = WM2200_DSP1_CONTROL_1; in wm2200_i2c_probe()
2217 wm2200->dsp[0].cs_dsp.mem = wm2200_dsp1_regions; in wm2200_i2c_probe()
2218 wm2200->dsp[0].cs_dsp.num_mems = ARRAY_SIZE(wm2200_dsp1_regions); in wm2200_i2c_probe()
2220 wm2200->dsp[1].cs_dsp.base = WM2200_DSP2_CONTROL_1; in wm2200_i2c_probe()
2221 wm2200->dsp[1].cs_dsp.mem = wm2200_dsp2_regions; in wm2200_i2c_probe()
2222 wm2200->dsp[1].cs_dsp.num_mems = ARRAY_SIZE(wm2200_dsp2_regions); in wm2200_i2c_probe()
2224 for (i = 0; i < ARRAY_SIZE(wm2200->dsp); i++) in wm2200_i2c_probe()
2225 wm_adsp1_init(&wm2200->dsp[i]); in wm2200_i2c_probe()
2228 wm2200->pdata = *pdata; in wm2200_i2c_probe()
2232 for (i = 0; i < ARRAY_SIZE(wm2200->core_supplies); i++) in wm2200_i2c_probe()
2233 wm2200->core_supplies[i].supply = wm2200_core_supply_names[i]; in wm2200_i2c_probe()
2235 ret = devm_regulator_bulk_get(&i2c->dev, in wm2200_i2c_probe()
2236 ARRAY_SIZE(wm2200->core_supplies), in wm2200_i2c_probe()
2237 wm2200->core_supplies); in wm2200_i2c_probe()
2239 dev_err(&i2c->dev, "Failed to request core supplies: %d\n", in wm2200_i2c_probe()
2244 ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies), in wm2200_i2c_probe()
2245 wm2200->core_supplies); in wm2200_i2c_probe()
2247 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n", in wm2200_i2c_probe()
2252 wm2200->ldo_ena = devm_gpiod_get_optional(&i2c->dev, "wlf,ldo1ena", in wm2200_i2c_probe()
2254 if (IS_ERR(wm2200->ldo_ena)) { in wm2200_i2c_probe()
2255 ret = PTR_ERR(wm2200->ldo_ena); in wm2200_i2c_probe()
2256 dev_err(&i2c->dev, "Failed to request LDOENA GPIO %d\n", in wm2200_i2c_probe()
2260 if (wm2200->ldo_ena) { in wm2200_i2c_probe()
2261 gpiod_set_consumer_name(wm2200->ldo_ena, "WM2200 LDOENA"); in wm2200_i2c_probe()
2265 wm2200->reset = devm_gpiod_get_optional(&i2c->dev, "reset", in wm2200_i2c_probe()
2267 if (IS_ERR(wm2200->reset)) { in wm2200_i2c_probe()
2268 ret = PTR_ERR(wm2200->reset); in wm2200_i2c_probe()
2269 dev_err(&i2c->dev, "Failed to request RESET GPIO %d\n", in wm2200_i2c_probe()
2273 gpiod_set_consumer_name(wm2200->reset, "WM2200 /RESET"); in wm2200_i2c_probe()
2275 ret = regmap_read(wm2200->regmap, WM2200_SOFTWARE_RESET, ®); in wm2200_i2c_probe()
2277 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); in wm2200_i2c_probe()
2285 dev_err(&i2c->dev, "Device is not a WM2200, ID is %x\n", reg); in wm2200_i2c_probe()
2286 ret = -EINVAL; in wm2200_i2c_probe()
2290 ret = regmap_read(wm2200->regmap, WM2200_DEVICE_REVISION, ®); in wm2200_i2c_probe()
2292 dev_err(&i2c->dev, "Failed to read revision register\n"); in wm2200_i2c_probe()
2296 wm2200->rev = reg & WM2200_DEVICE_REVISION_MASK; in wm2200_i2c_probe()
2298 dev_info(&i2c->dev, "revision %c\n", wm2200->rev + 'A'); in wm2200_i2c_probe()
2300 switch (wm2200->rev) { in wm2200_i2c_probe()
2303 ret = regmap_register_patch(wm2200->regmap, wm2200_reva_patch, in wm2200_i2c_probe()
2306 dev_err(&i2c->dev, "Failed to register patch: %d\n", in wm2200_i2c_probe()
2316 dev_err(&i2c->dev, "Failed to issue reset\n"); in wm2200_i2c_probe()
2320 for (i = 0; i < ARRAY_SIZE(wm2200->pdata.gpio_defaults); i++) { in wm2200_i2c_probe()
2321 if (!wm2200->pdata.gpio_defaults[i]) in wm2200_i2c_probe()
2324 regmap_write(wm2200->regmap, WM2200_GPIO_CTRL_1 + i, in wm2200_i2c_probe()
2325 wm2200->pdata.gpio_defaults[i]); in wm2200_i2c_probe()
2329 regmap_update_bits(wm2200->regmap, wm2200_dig_vu[i], in wm2200_i2c_probe()
2332 /* Assign slots 1-6 to channels 1-6 for both TX and RX */ in wm2200_i2c_probe()
2334 regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_10 + i, i); in wm2200_i2c_probe()
2335 regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i); in wm2200_i2c_probe()
2339 if (!wm2200->pdata.micbias[i].mb_lvl && in wm2200_i2c_probe()
2340 !wm2200->pdata.micbias[i].bypass) in wm2200_i2c_probe()
2344 if (!wm2200->pdata.micbias[i].mb_lvl) in wm2200_i2c_probe()
2345 wm2200->pdata.micbias[i].mb_lvl in wm2200_i2c_probe()
2348 val = (wm2200->pdata.micbias[i].mb_lvl -1) in wm2200_i2c_probe()
2351 if (wm2200->pdata.micbias[i].discharge) in wm2200_i2c_probe()
2354 if (wm2200->pdata.micbias[i].fast_start) in wm2200_i2c_probe()
2357 if (wm2200->pdata.micbias[i].bypass) in wm2200_i2c_probe()
2360 regmap_update_bits(wm2200->regmap, in wm2200_i2c_probe()
2368 for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) { in wm2200_i2c_probe()
2369 regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i], in wm2200_i2c_probe()
2372 (wm2200->pdata.in_mode[i] << in wm2200_i2c_probe()
2374 (wm2200->pdata.dmic_sup[i] << in wm2200_i2c_probe()
2378 if (i2c->irq) { in wm2200_i2c_probe()
2379 ret = request_threaded_irq(i2c->irq, NULL, wm2200_irq, in wm2200_i2c_probe()
2383 regmap_update_bits(wm2200->regmap, in wm2200_i2c_probe()
2387 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", in wm2200_i2c_probe()
2388 i2c->irq, ret); in wm2200_i2c_probe()
2391 pm_runtime_set_active(&i2c->dev); in wm2200_i2c_probe()
2392 pm_runtime_enable(&i2c->dev); in wm2200_i2c_probe()
2393 pm_request_idle(&i2c->dev); in wm2200_i2c_probe()
2395 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_wm2200, in wm2200_i2c_probe()
2398 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); in wm2200_i2c_probe()
2405 pm_runtime_disable(&i2c->dev); in wm2200_i2c_probe()
2406 if (i2c->irq) in wm2200_i2c_probe()
2407 free_irq(i2c->irq, wm2200); in wm2200_i2c_probe()
2409 gpiod_set_value_cansleep(wm2200->reset, 1); in wm2200_i2c_probe()
2411 gpiod_set_value_cansleep(wm2200->ldo_ena, 0); in wm2200_i2c_probe()
2413 regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies), in wm2200_i2c_probe()
2414 wm2200->core_supplies); in wm2200_i2c_probe()
2422 pm_runtime_disable(&i2c->dev); in wm2200_i2c_remove()
2423 if (i2c->irq) in wm2200_i2c_remove()
2424 free_irq(i2c->irq, wm2200); in wm2200_i2c_remove()
2426 gpiod_set_value_cansleep(wm2200->reset, 1); in wm2200_i2c_remove()
2427 gpiod_set_value_cansleep(wm2200->ldo_ena, 0); in wm2200_i2c_remove()
2428 regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies), in wm2200_i2c_remove()
2429 wm2200->core_supplies); in wm2200_i2c_remove()
2437 regcache_cache_only(wm2200->regmap, true); in wm2200_runtime_suspend()
2438 regcache_mark_dirty(wm2200->regmap); in wm2200_runtime_suspend()
2439 gpiod_set_value_cansleep(wm2200->ldo_ena, 0); in wm2200_runtime_suspend()
2440 regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies), in wm2200_runtime_suspend()
2441 wm2200->core_supplies); in wm2200_runtime_suspend()
2451 ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies), in wm2200_runtime_resume()
2452 wm2200->core_supplies); in wm2200_runtime_resume()
2459 if (wm2200->ldo_ena) { in wm2200_runtime_resume()
2460 gpiod_set_value_cansleep(wm2200->ldo_ena, 1); in wm2200_runtime_resume()
2464 regcache_cache_only(wm2200->regmap, false); in wm2200_runtime_resume()
2465 regcache_sync(wm2200->regmap); in wm2200_runtime_resume()